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    Semiconductor memory device and data read method of the same
    4.
    发明申请
    Semiconductor memory device and data read method of the same 失效
    半导体存储器件和数据读取方法相同

    公开(公告)号：US20050122830A1

    公开(公告)日：2005-06-09

    申请号：US10993577

    申请日：2004-11-19

    申请人： Myeong-O Kim ,  Sung-Min Seo

    发明人： Myeong-O Kim ,  Sung-Min Seo

    IPC分类号： G11C11/40 ,  G11C7/10 ,  G11C8/00

    CPC分类号： G11C7/04 ,  G11C7/1042 ,  G11C7/1066 ,  G11C2207/2281

    摘要： The present invention discloses a semiconductor memory device that includes first and second memory banks. A first control signal generating circuit generates a first control signal responsive to an external clock. A first data output circuit transmits a first output data responsive to the first control signal. An internal clock signal generating circuit outputs first and second buffered clock signals responsive to the external clock. A second control signal generating circuit generates a second control signal responsive to the first buffered clock signal and the first control signal. A second data output circuit transmits a second output data responsive to the second control signal. A third data output circuit transmits a third output data responsive to the first and second buffered clock signals. The present invention prevents data read errors resulting from variations in power supply voltage and temperature.

    摘要翻译： 本发明公开了一种包括第一和第二存储体的半导体存储器件。 第一控制信号产生电路响应外部时钟产生第一控制信号。 第一数据输出电路响应于第一控制信号发送第一输出数据。 内部时钟信号发生电路响应于外部时钟输出第一和第二缓冲时钟信号。 第二控制信号发生电路响应于第一缓冲时钟信号和第一控制信号产生第二控制信号。 第二数据输出电路响应于第二控制信号发送第二输出数据。 第三数据输出电路响应于第一和第二缓冲时钟信号发送第三输出数据。 本发明防止由电源电压和温度变化引起的数据读取错误。

    Semiconductor memory devices having separate read and write global data lines
    6.
    发明授权
    Semiconductor memory devices having separate read and write global data lines 失效
    半导体存储器件具有单独的读和写全局数据线

    公开(公告)号：US07184347B2

    公开(公告)日：2007-02-27

    申请号：US11186691

    申请日：2005-07-21

    申请人： Jae-Young Lee ,  Chi Wook Kim ,  Sung-Min Seo

    发明人： Jae-Young Lee ,  Chi Wook Kim ,  Sung-Min Seo

    IPC分类号： G11C7/02

    CPC分类号： G11C7/10 ,  G11C7/18

    摘要： Semiconductor memory devices include a memory cell array region having a plurality of memory cells, a local data I/O line pair that is electrically connected to the plurality of memory cells, a local sense amplifier that is electrically connected to the local data I/O line pair, a read global data I/O line pair that is electrically connected to the local sense amplifier and that is configured to transmit data during a read operation and a write global data I/O line pair that is electrically connected to the local sense amplifier that is configured to transmit data during a write operation.

    摘要翻译： 半导体存储器件包括具有多个存储器单元的存储单元阵列区域，电连接到多个存储单元的本地数据I / O线对，与本地数据I / O电连接的本地读出放大器 线对，读取的全局数据I / O线对，其被电连接到本地读出放大器，并且被配置为在读取操作期间传输数据，并且写入全局数据I / O线对被电连接到本地感测 配置为在写入操作期间传输数据的放大器。

    Semiconductor memory device and data read method of the same
    7.
    发明授权
    Semiconductor memory device and data read method of the same 失效
    半导体存储器件和数据读取方法相同

    公开(公告)号：US07106653B2

    公开(公告)日：2006-09-12

    申请号：US10993577

    申请日：2004-11-19

    申请人： Myeong-O Kim ,  Sung-Min Seo

    发明人： Myeong-O Kim ,  Sung-Min Seo

    IPC分类号： G11C8/00

    CPC分类号： G11C7/04 ,  G11C7/1042 ,  G11C7/1066 ,  G11C2207/2281

    摘要： The present invention discloses a semiconductor memory device that includes first and second memory banks. A first control signal generating circuit generates a first control signal responsive to an external clock. A first data output circuit transmits a first output data responsive to the first control signal. An internal clock signal generating circuit outputs first and second buffered clock signals responsive to the external clock. A second control signal generating circuit generates a second control signal responsive to the first buffered clock signal and the first control signal. A second data output circuit transmits a second output data responsive to the second control signal. A third data output circuit transmits a third output data responsive to the first and second buffered clock signals. The present invention prevents data read errors resulting from variations in power supply voltage and temperature.

    摘要翻译： 本发明公开了一种包括第一和第二存储体的半导体存储器件。 第一控制信号产生电路响应外部时钟产生第一控制信号。 第一数据输出电路响应于第一控制信号发送第一输出数据。 内部时钟信号发生电路响应于外部时钟输出第一和第二缓冲时钟信号。 第二控制信号发生电路响应于第一缓冲时钟信号和第一控制信号产生第二控制信号。 第二数据输出电路响应于第二控制信号发送第二输出数据。 第三数据输出电路响应于第一和第二缓冲时钟信号发送第三输出数据。 本发明防止由电源电压和温度变化引起的数据读取错误。

    Redundancy repair circuit and a redundancy repair method therefor
    8.
    发明申请
    Redundancy repair circuit and a redundancy repair method therefor 有权
    冗余修复电路及冗余修复方法

    公开(公告)号：US20050270863A1

    公开(公告)日：2005-12-08

    申请号：US11092097

    申请日：2005-03-29

    申请人： Jun-Hyung Kim ,  Chi-Wook Kim ,  Sung-Min Seo

    发明人： Jun-Hyung Kim ,  Chi-Wook Kim ,  Sung-Min Seo

    IPC分类号： G11C7/00 ,  G11C29/00

    CPC分类号： G11C29/802

    摘要： A redundancy repair circuit and method therefor for use with a semiconductor memory device are provided. The redundancy repair circuit comprises: a memory circuit having a plurality of address lines and a plurality of redundancy address lines in a memory cell; a repair redundancy control circuit for repairing a defective address line using a redundancy address line of the plurality of redundancy address lines, and for encoding and outputting fuse repair information corresponding to redundancy address information, wherein addresses corresponding to defective memory cells are pre-programmed; and a redundancy line driver for receiving the fuse repair information from the repair redundancy control circuit, for decoding the fuse repair information and for activating a redundancy line corresponding to the decoded fuse repair information, wherein the repair redundancy control circuit is separate from the redundancy line driver.

    摘要翻译： 提供了一种与半导体存储器件一起使用的冗余修复电路及其方法。 冗余修复电路包括：在存储单元中具有多个地址线和多个冗余地址线的存储器电路; 修复冗余控制电路，用于使用所述多个冗余地址线的冗余地址线修复缺陷地址线，以及用于编码和输出与冗余地址信息相对应的保险丝修复信息，其中与缺陷存储器单元相对应的地址被预编程; 以及冗余线路驱动器，用于从所述修复冗余控制电路接收所述保险丝修复信息，用于解码所述保险丝修复信息并用于激活对应于所述解码的熔丝修复信息的冗余线，其中所述修复冗余控制电路与所述冗余线分离 司机。