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公开(公告)号：US07378317B2
公开(公告)日：2008-05-27
申请号：US11304196
申请日：2005-12-14
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/7809 , H01L29/7811
摘要： Methods and apparatus are provided for TMOS devices, comprising multiple N-type source regions, electrically in parallel, located in multiple P-body regions separated by N-type JFET regions at a first surface. The gate overlies the body channel regions and the JFET region lying between the body regions. The JFET region communicates with an underlying drain region via an N-epi region. Ion implantation and heat treatment are used to tailor the net active doping concentration Nd in the JFET region of length Lacc and net active doping concentration Na in the P-body regions of length Lbody so that a charge balance relationship (Lbody*Na)=k1*(Lacc*Nd) between P-body and JFET regions is satisfied, where k1 is about 0.6≦k1≦1.4. The entire device can be fabricated using planar technology and the charge balanced regions need not extend through the underlying N-epi region to the drain.
摘要翻译： 提供了用于TMOS器件的方法和装置，其包括并联的多个N型源极区域，位于在第一表面处由N型JFET区域分离的多个P体区域中。 栅极覆盖身体通道区域和位于身体区域之间的JFET区域。 JFET区域经由N-epi区域与下面的漏极区域连通。 离子注入和热处理用于定制长度为L的JFET区域中的净有源掺杂浓度N sub和净活性掺杂浓度N a， 在长度为L <！ - SIPO
- >本体的P体区域中，电荷平衡关系（L <！ - SIPO - >） 满足P体和JFET区之间的> 1 *（L N N D D），其中k 1是约 0.6 <= K 1 <= 1.4。 整个器件可以使用平面技术制造，并且电荷平衡区域不需要延伸通过下面的N-epi区域到漏极。 -
公开(公告)号：US07598517B2
公开(公告)日：2009-10-06
申请号：US11510547
申请日：2006-08-25
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1054 , H01L29/165 , H01L29/42368 , H01L29/66734
摘要： Semiconductor structures and methods are provided for a semiconductor device (40) employing a superjunction structure (41) and overlying trench (91) with embedded control gate (48). The method comprises, forming (52-6, 52-9) interleaved first (70-1, 70-2, 70-3, 70-4, etc.) and second (74-1, 74-2, 74-3, etc.) spaced-apart regions of first (70) and second (74) semiconductor materials of different conductivity type and different mobilities so that, in a first embodiment, the second semiconductor material (74) has a higher mobility for the same carrier type than the first semiconductor material (70), and providing (52-14) an overlying third semiconductor material (82) in which a trench (90, 91) is formed with sidewalls (913) having thereon a fourth semiconductor material (87) that has a higher mobility than the third material (82), adapted to carry current (50) between source regions (86), through the fourth (87) semiconductor material in the trench (91) and the second semiconductor material (74) in the device drift space (42) to the drain (56). In a further embodiment, the first (70) and third (82) semiconductor materials are relaxed materials and the second (74) and fourth (87) semiconductor materials are strained semiconductor materials.
摘要翻译： 为半导体器件（40）提供半导体结构和方法，该半导体器件采用超结构结构（41）和具有嵌入式控制栅极（48）的上覆沟槽（91）。 该方法包括：首先（70-1,70-2,70-3,70-4等）和第二（74-1,74-2,74-3）交错形成（52-6,52-9） 等等）具有不同导电类型和不同迁移率的第一（70）和第二（74）半导体材料的间隔开的区域，使得在第一实施例中，第二半导体材料（74）对于相同载体具有较高的迁移率 并且提供（52-14）上覆第三半导体材料（82），其中沟槽（90,91）形成有其上具有第四半导体材料（87）的侧壁（913） 其具有比第三材料（82）更高的迁移率，其适于在源极区域（86）之间通过沟槽（91）中的第四（87）半导体材料和第二半导体材料（74）中承载电流（50） 设备漂移空间（42）到排水管（56）。 在另一实施例中，第一（70）和第三（82）半导体材料是松弛材料，第二（74）和第四（87）半导体材料是应变半导体材料。
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公开(公告)号：US20090286372A1
公开(公告)日：2009-11-19
申请号：US12511849
申请日：2009-07-29
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1054 , H01L29/165 , H01L29/42368 , H01L29/66734
摘要： Methods for forming semiconductor structures are provided for a semiconductor device employing a superjunction structure and overlying trench with embedded control gate. An embodiment comprises forming interleaved first and second spaced-apart regions of first and second semiconductor materials of different conductivity type and different mobilities so that the second semiconductor material has a higher mobility for the same carrier type than the first semiconductor material, and providing an overlying third semiconductor material in which a trench is formed with sidewalls having thereon a fourth semiconductor material that has a higher mobility than the third material, adapted to carry current between source regions, through the fourth semiconductor material in the trench and the second semiconductor material in the device drift space to the drain. In a further embodiment, the first and third semiconductor materials are relaxed materials and the second and fourth semiconductor materials are strained semiconductor materials.
摘要翻译： 为半导体器件提供了形成半导体结构的方法，该半导体器件采用超结构结构和具有嵌入式控制栅极的上覆沟槽。 一个实施例包括形成具有不同导电类型和不同迁移率的第一和第二半导体材料的交错的第一和第二间隔开的区域，使得第二半导体材料对于与第一半导体材料相同的载体类型具有较高的迁移率，并提供覆盖 第三半导体材料，其中沟槽形成有侧壁，其上具有第四半导体材料，第四半导体材料具有比第三材料更高的迁移率，适于在源极区域之间通过沟槽中的第四半导体材料和第二半导体材料中的第二半导体材料 器件漂移空间到漏极。 在另一个实施例中，第一和第三半导体材料是松弛材料，第二和第四半导体材料是应变半导体材料。
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公开(公告)号：US07592230B2
公开(公告)日：2009-09-22
申请号：US11510552
申请日：2006-08-25
IPC分类号： H01L21/336
CPC分类号： H01L29/66348 , H01L29/73 , H01L29/7397
摘要： Means and methods are provided for trench TMOS devices (41-10, 11, 12), comprising, providing a first semiconductor (53, 53′) of a first composition having an upper surface (541), with a body portion (54) proximate the upper surface (541), a drift portion (46, 83) spaced apart from the upper surface (541) and a trench (49, 49′) having sidewalls (493) extending from the upper surface (541) into the drift portion (46, 83). A second semiconductor (56) adapted to provide a higher mobility layer is applied on the trench sidewalls (493) where parts (78) of the body portion (54) are exposed. A dielectric (70) covers the higher mobility layer (56) and separates it from a control gate (72) in the trench (49, 49′). Source regions (68) formed in the body portion (54) proximate the upper surface (491) communicate with the higher mobility layer (56). When biased, source-drain current (87, 87′) flows from the source regions (68) through gate induced channels (78) in the higher mobility layer (56) and into the drift portion (46, 83) where it is extracted by a drain (42) or other connection coupled to the drift portion (46, 83).
摘要翻译： 提供了用于沟槽TMOS器件（41-10,11,12）的方法和方法，包括：提供具有上表面（541）的第一组合物的第一半导体（53,53'）与主体部分（54） 邻近上表面（541），与上表面（541）间隔开的漂移部分（46,83）和具有从上表面（541）延伸到漂移体（491）中的侧壁（493）的沟槽 部分（46,83）。 适于提供更高迁移率层的第二半导体（56）被施加在主体部分（54）的部分（78）暴露的沟槽侧壁（493）上。 电介质（70）覆盖高迁移率层（56）并将其与沟槽（49,49'）中的控制栅极（72）分离。 形成在靠近上表面（491）的主体部分（54）中的源区（68）与较高迁移率层（56）连通。 当偏置时，源极 - 漏极电流（87,87'）从源极区（68）流过高迁移率层（56）中的栅极感应通道（78）并流入其中被提取的漂移部分（46,83） 通过连接到漂移部分（46,83）的排水（42）或其它连接。
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公开(公告)号：US07651918B2
公开(公告)日：2010-01-26
申请号：US11510541
申请日：2006-08-25
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/165 , H01L29/456 , H01L29/66719 , Y10S438/912
摘要： Semiconductor structures (52-9, 52-11, 52-12) and methods (100-300) are provided for a semiconductor devices employing strained (70) and relaxed (66) semiconductors, The method comprises, forming (106, 208, 308) on a substrate (54, 56, 58) first (66-1) and second (66-2) regions of a first semiconductor material (66) of a first conductivity type and a first lattice constant spaced apart by a gap or trench (69), filling (108, 210, 308) the trench or gap (69) with a second semiconductor material (70) of a second, conductivity type and a second different lattice constant so that the second semiconductor material (70) is strained with respect to the first semiconductor material (66) and forming (110, 212, 312) device regions (80, 88, S, G, D) communicating with the first (66) and second (70) semiconductor materials and adapted to provide device current (87, 87′) through at least part of the strained second semiconductor material (70) in the trench (69). In a preferred embodiment, the relaxed semiconductor material is 80:20 Si:Ge and the strained semiconductor material is substantially Si.
摘要翻译： 半导体结构（52-9,52-11,52-12）和方法（100-300）用于采用应变（70）和松弛（66）半导体的半导体器件。该方法包括：形成（106,208， 第一导电类型的第一半导体材料（66）的第一（66-1）和第二（66-2）区域和由间隙间隔开的第一晶格常数的衬底（54,56,58）上， 沟槽（69），用第二导电类型和第二不同晶格常数的第二半导体材料（70）填充（108,210,308）沟槽或间隙（69），使得第二半导体材料（70）为 相对于第一半导体材料（66）应变并且与第一（66）和第二（70）半导体材料连通并形成（110,212,312）器件区域（80,88，S，G，D） 通过沟槽（69）中的应变第二半导体材料（70）的至少一部分提供器件电流（87,87'）。 在优选实施例中，松弛的半导体材料是80:20的Si：Ge，应变半导体材料基本上是Si。
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公开(公告)号：US07602014B2
公开(公告)日：2009-10-13
申请号：US12109215
申请日：2008-04-24
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/7809 , H01L29/7811
摘要： An embodiment of an MOS device includes a semiconductor substrate of a first conductivity type, a first region of the first conductivity type having a length Lacc and a net active dopant concentration of about Nfirst, a pair of spaced-apart body regions of a second opposite conductivity type and each having a length Lbody and a net active dopant concentration of about Nsecond, channel regions located in the spaced-apart body regions, source regions of the first conductivity type located in the spaced-apart body regions and separated from the first region by the channel regions, an insulated gate overlying the channel regions and the first region, and a drain region of the first conductivity type located beneath the first region. In an embodiment, (Lbody*Nsecond)=k1*(Lacc*Nfirst), where k1 has a value in the range of about 0.6≦k1≦1.4.
摘要翻译： MOS器件的实施例包括第一导电类型的半导体衬底，具有长度Lacc的第一导电类型的第一区域和约Nfirst的净有源掺杂剂浓度，一对间隔开的体区域，第二相对的 导电类型，并且每个具有约N秒的长度Lbody和净活性掺杂剂浓度，位于间隔开的体区中的沟道区，位于间隔开的体区中的第一导电类型的源区，并与第一区分离 通过沟道区域，覆盖沟道区域和第一区域的绝缘栅极以及位于第一区域下方的第一导电类型的漏极区域。 在一个实施例中，（Lbody * Nsecond）= k1 *（Lacc * Nfirst），其中k1具有在大约0.6 <= k1 <= 1.4的范围内的值。
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公开(公告)号：US20080197409A1
公开(公告)日：2008-08-21
申请号：US12109215
申请日：2008-04-24
IPC分类号： H01L29/10
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/7809 , H01L29/7811
摘要： An embodiment of an MOS device includes a semiconductor substrate of a first conductivity type, a first region of the first conductivity type having a length Lacc and a net active dopant concentration of about Nfirst, a pair of spaced-apart body regions of a second opposite conductivity type and each having a length Lbody and a net active dopant concentration of about Nsecond, channel regions located in the spaced-apart body regions, source regions of the first conductivity type located in the spaced-apart body regions and separated from the first region by the channel regions, an insulated gate overlying the channel regions and the first region, and a drain region of the first conductivity type located beneath the first region. In an embodiment, (Lbody*Nsecond)=k1*(Lacc*Nfirst), where k1 has a value in the range of about 0.6≦k1≦1.4.
摘要翻译： MOS器件的一个实施例包括具有第一导电类型的半导体衬底，第一导电类型的第一区域具有长度L <！ - SIPO
第二个）= k 1 *（L >第一），其中k <1>具有在大约0.6≤K≤1的范围内的值。 -
公开(公告)号：US07834417B2
公开(公告)日：2010-11-16
申请号：US12413078
申请日：2009-03-27
申请人： Won Gi Min , Robert W. Baird , Gordon P. Lee , Jiang-Kai Zuo
发明人： Won Gi Min , Robert W. Baird , Gordon P. Lee , Jiang-Kai Zuo
CPC分类号： H01L23/5252 , H01L27/112 , H01L27/11206 , H01L2924/0002 , Y10S438/981 , H01L2924/00
摘要： An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) includes a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) includes one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) is defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).
摘要翻译： 反熔断元件（102,152,252,302,352,402,602,652,702）包括具有形成在上表面中的有源区（106）的衬底材料（101），栅电极（104） 位于有源区域（106）上方的至少一部分，和设置在栅电极（104）和有源区域（106）之间的栅极氧化物层（110）。 栅极氧化物层（110）包括栅极氧化物浸渍（128）或栅极氧化物底切（614）之一。 在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过栅极氧化物层（110）的电流路径以及在破裂区域（130）中的栅极氧化物层（110）的破裂。 破裂区域（130）由氧化物结构和栅极氧化物浸渍（128）或栅极氧化物底切（614）限定。
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9.发明申请Electronic assembly having magnetic tunnel junction voltage sensors and method for forming the same 审中-公开具有磁隧道结电压传感器的电子组件及其形成方法公开(公告)号：US20080112214A1
公开(公告)日：2008-05-15
申请号：US11590276
申请日：2006-10-30
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Pon Sung Ku
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Pon Sung Ku
CPC分类号： H01L27/088 , B82Y25/00 , G11C11/16 , H01L27/0623 , H01L27/228
摘要： A method and assembly for sensing a voltage with a memory cell (88) is provided. The memory cell includes first and second electrodes (96,112), first and second ferromagnetic bodies (104,108) positioned between the first and second electrodes and an insulating body (94) positioned between the first and second ferromagnetic bodies. The first electrode is electrically connected to a first portion of a microelectronic assembly (47). The second electrode is electrically connected to a second portion of the microelectronic assembly. The voltage across the first and second portions of the microelectronic assembly is determined based on an electrical resistance of the memory cell. The memory cell may be a magnetoresistive random access memory (MRAM) cell. In one embodiment, the memory cell is a magnetic tunnel junction (MTJ) memory cell.
摘要翻译： 提供了一种用于利用存储单元（88）感测电压的方法和组件。 存储单元包括位于第一和第二电极之间的第一和第二电极（96,112），第一和第二铁磁体（104,108）和位于第一和第二铁磁体之间的绝缘体（94）。 第一电极电连接到微电子组件（47）的第一部分。 第二电极电连接到微电子组件的第二部分。 基于存储单元的电阻来确定微电子组件的第一和第二部分两端的电压。 存储单元可以是磁阻随机存取存储器（MRAM）单元。 在一个实施例中，存储器单元是磁性隧道结（MTJ）存储单元。
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公开(公告)号：US20080048257A1
公开(公告)日：2008-02-28
申请号：US11510541
申请日：2006-08-25
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/165 , H01L29/456 , H01L29/66719 , Y10S438/912
摘要： Semiconductor structures (52-9, 52-11, 52-12) and methods (100-300) are provided for a semiconductor devices employing strained (70) and relaxed (66) semiconductors, The method comprises, forming (106, 208, 308) on a substrate (54, 56, 58) first (66-1) and second (66-2) regions of a first semiconductor material (66) of a first conductivity type and a first lattice constant spaced apart by a gap or trench (69), filling (108, 210, 308) the trench or gap (69) with a second semiconductor material (70) of a second, conductivity type and a second different lattice constant so that the second semiconductor material (70) is strained with respect to the first semiconductor material (66) and forming (110, 212, 312) device regions (80, 88, S, G, D) communicating with the first (66) and second (70) semiconductor materials and adapted to provide device current (87, 87′) through at least part of the strained second semiconductor material (70) in the trench (69). In a preferred embodiment, the relaxed semiconductor material is 80:20 Si:Ge and the strained semiconductor material is substantially Si.
摘要翻译： 为使用应变（70）和松弛（66）半导体的半导体器件提供半导体结构（52-9,52-11,222）和方法（100-300）。该方法包括：形成（106,208， 第一导电类型的第一半导体材料（66）的第一（66-1）和第二（66-2）区域和由间隙间隔开的第一晶格常数的衬底（54,56,58）上， 沟槽（69），用第二导电类型和第二不同晶格常数的第二半导体材料（70）填充（108,210,308）沟槽或间隙（69），使得第二半导体材料（70）为 相对于第一半导体材料（66）应变并且与第一（66）和第二（70）半导体材料连通并形成（110,212,312）器件区域（80,88，S，G，D） 通过t中的应变第二半导体材料（70）的至少一部分提供器件电流（87,87'） 他沟渠（69）。 在优选实施例中，松弛的半导体材料是80:20的Si：Ge，应变半导体材料基本上是Si。
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