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    Digital PLL with automatic clock alignment
    1.
    发明授权
    Digital PLL with automatic clock alignment 失效
    数字PLL与自动时钟对齐

    公开(公告)号：US08373472B2

    公开(公告)日：2013-02-12

    申请号：US13164096

    申请日：2011-06-20

    Applicant: Edwin Thaller ,  Stefano Marsili ,  Giuseppe Li Puma

    Inventor： Edwin Thaller ,  Stefano Marsili ,  Giuseppe Li Puma

    IPC: H03L7/06

    CPC classification number: H03L7/183

    Abstract: One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies. A clock aligner monitors a phase difference between the variable clock signal and one of the plurality of time-aligned output clock signals and generates a control signal that causes a programmable delay line to automatically time-align the output clock signals with the variable clock signal.

    Abstract translation: 本发明的一个实施例涉及一种被配置为产生具有不同频率值的多个时间对齐的输出时钟信号的数字锁相环（ADPLL）。 ADPLL包括数字控制振荡器，其被配置为产生可变时钟信号，该可变时钟信号被分成根据两个分离的时钟域操作的两个信号路径。 第一信号路径被配置为产生使可变时钟信号与参考信号同步的反馈信号。 第二信号路径包括时钟分频器电路，其被配置为对可变时钟信号进行同步分频，以自动生成具有不同频率的多个时间对齐的输出时钟信号。 时钟对准器监视可变时钟信号和多个时间对齐的输出时钟信号中的一个之间的相位差，并产生使可编程延迟线自动将输出时钟信号与可变时钟信号时间对准的控制信号。

    DIGITAL PLL WITH AUTOMATIC CLOCK ALIGNMENT
    3.
    发明申请
    DIGITAL PLL WITH AUTOMATIC CLOCK ALIGNMENT 失效
    数字PLL与自动时钟对准

    公开(公告)号：US20120319749A1

    公开(公告)日：2012-12-20

    申请号：US13164096

    申请日：2011-06-20

    Applicant: Edwin Thaller ,  Stefano Marsili ,  Giuseppe Li Puma

    Inventor： Edwin Thaller ,  Stefano Marsili ,  Giuseppe Li Puma

    IPC: H03L7/06

    CPC classification number: H03L7/183

    Abstract: One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies. A clock aligner monitors a phase difference between the variable clock signal and one of the plurality of time-aligned output clock signals and generates a control signal that causes a programmable delay line to automatically time-align the output clock signals with the variable clock signal.

    Abstract translation: 本发明的一个实施例涉及一种被配置为产生具有不同频率值的多个时间对齐的输出时钟信号的数字锁相环（ADPLL）。 ADPLL包括数字控制振荡器，其被配置为产生可变时钟信号，该可变时钟信号被分成根据两个分离的时钟域操作的两个信号路径。 第一信号路径被配置为产生使可变时钟信号与参考信号同步的反馈信号。 第二信号路径包括时钟分频器电路，其被配置为对可变时钟信号进行同步分频，以自动生成具有不同频率的多个时间对齐的输出时钟信号。 时钟对准器监视可变时钟信号和多个时间对齐的输出时钟信号中的一个之间的相位差，并产生使可编程延迟线自动将输出时钟信号与可变时钟信号时间对准的控制信号。

    CIRCUIT WITH NOISE SHAPER
    4.
    发明申请
    CIRCUIT WITH NOISE SHAPER 审中-公开
    电路与噪音形状

    公开(公告)号：US20120049907A1

    公开(公告)日：2012-03-01

    申请号：US13289858

    申请日：2011-11-04

    Applicant: Nicola Da Dalt ,  Edwin Thaller

    Inventor： Nicola Da Dalt ,  Edwin Thaller

    IPC: H03L7/08

    CPC classification number: H03L7/16 ,  H03L2207/50

    Abstract: In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping.

    Abstract translation: 在一个实施例中，提供了包括振荡器的电路。 基于反馈值和输入参考值来控制振荡器。 使用噪声整形产生反馈值或参考值或两者。

    Method and device for extracting a clock frequency underlying a data stream
    6.
    发明授权
    Method and device for extracting a clock frequency underlying a data stream 失效
    用于提取数据流下的时钟频率的方法和装置

    公开(公告)号：US07453958B2

    公开(公告)日：2008-11-18

    申请号：US11166657

    申请日：2005-06-23

    Applicant: Patrizia Greco ,  Andreas Steinschaden ,  Edwin Thaller ,  Gernot Zessar

    Inventor： Patrizia Greco ,  Andreas Steinschaden ,  Edwin Thaller ,  Gernot Zessar

    IPC: H04L27/00

    CPC classification number: H03L7/0995 ,  H03L2207/50 ,  H04L7/046

    Abstract: A device for extracting a clock frequency underlying a data stream includes means for controlling a controllable oscillator, coarse-tuning means and fine-tuning means, wherein coarse-tuning means responds to a second data pattern present in the data stream and sets the oscillator coarsely based on its length. Fine-tuning means responds to temporally consecutive first data patterns present in the data stream with a higher accuracy in order to perform a fine tuning of the oscillator on the basis of the temporal length between the two first data patterns and on the basis of the number of clock cycles of the controllable oscillator occurring in this temporal length.

    Abstract translation: 用于提取数据流下面的时钟频率的装置包括用于控制可控振荡器的装置，粗调谐装置和微调装置，其中粗调装置响应数据流中存在的第二数据模式并将振荡器粗略地设置 基于它的长度。 微调装置以更高的精度响应存在于数据流中的时间上连续的第一数据模式，以便基于两个第一数据模式之间的时间长度并基于数量来执行振荡器的微调 可控振荡器的时钟周期在该时间长度上发生。

    Digitally controllable oscillator
    7.
    发明授权
    Digitally controllable oscillator 有权
    数字可控振荡器

    公开(公告)号：US07081583B2

    公开(公告)日：2006-07-25

    申请号：US11166685

    申请日：2005-06-23

    Applicant: Patrizia Greco ,  Andreas Steinschaden ,  Edwin Thaller ,  Gernot Zessar

    Inventor： Patrizia Greco ,  Andreas Steinschaden ,  Edwin Thaller ,  Gernot Zessar

    IPC: G10H5/00

    CPC classification number: H03L7/0995 ,  H03L2207/50

    Abstract: A digitally controllable oscillator includes an oscillation generation means and an oscillator control, wherein the oscillator control comprises two digital/analog converters whose output signals are combined by a combiner in order to generate an analog input signal into the oscillation generation means. The second digital/analog converter is implemented in order to provide, in response to a digital increment in its digital input signal, a difference in the output signal of the second digital/analog converter which is smaller than a difference in the output signal of the first digital/analog converter when the first digital/analog converter is pulsed with the digital increment in its digital input signal.

    Abstract translation: 数字可控振荡器包括振荡发生装置和振荡器控制，其中振荡器控制包括两个数字/模拟转换器，其输出信号由组合器组合，以便产生到振荡产生装置中的模拟输入信号。 实现第二数字/模拟转换器以便响应于其数字输入信号中的数字增量来提供第二数/模转换器的输出信号的差值小于第二数/模转换器的输出信号的差值 第一个数字/模拟转换器，当第一个数字/模拟转换器在其数字输入信号中以数字增量脉冲。

    Polar transmitter suitable for monolithic integration in SoCs
    8.
    发明授权
    Polar transmitter suitable for monolithic integration in SoCs 有权
    极地发射器适用于SoC中的单片集成

    公开(公告)号：US08625708B2

    公开(公告)日：2014-01-07

    申请号：US12877188

    申请日：2010-09-08

    Applicant: Stefano Marsili ,  Giuseppe Li Puma ,  Stefan Van Waasen ,  Yanzhong Dai ,  Edwin Thaller

    Inventor： Stefano Marsili ,  Giuseppe Li Puma ,  Stefan Van Waasen ,  Yanzhong Dai ,  Edwin Thaller

    IPC: H04L27/00

    CPC classification number: H04L27/361 ,  H04B1/0475 ,  H04B1/0483

    Abstract: The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed.

    Abstract translation: 所公开的极性调制发射机电路被配置为产生具有最小化不同传输频带（例如，蓝牙，GSM，UMTS等）之间的串扰效应的传输频率的输出信号。 特别地，具有幅度调制（AM）信号和相位调制（PM）信号的极性调制收发器电路包括被配置为产生具有DCO频率的DCO信号的数字控制振荡器（DCO）。 DCO信号被提供给一个或多个分频器，其被配置为选择性地划分DCO信号以产生各种较低频率信号，用于选择在AM信号上操作的DAC的采样率和RF载波信号频率，其结果 在具有不干扰同一IC上的其它RF系统的频率的输出信号（例如，其落在其他RF系统的下行链路频率之外）。 还公开了其它系统和方法。

    Polar Transmitter Suitable for Monolithic Integration in SoCs
    9.
    发明申请
    Polar Transmitter Suitable for Monolithic Integration in SoCs 有权
    极地发射机适用于SoC中的整体集成

    公开(公告)号：US20120057655A1

    公开(公告)日：2012-03-08

    申请号：US12877188

    申请日：2010-09-08

    Applicant: Stefano Marsili ,  Giuseppe Li Puma ,  Stefan Van Waasen ,  Yanzhong Dai ,  Edwin Thaller

    Inventor： Stefano Marsili ,  Giuseppe Li Puma ,  Stefan Van Waasen ,  Yanzhong Dai ,  Edwin Thaller

    IPC: H04L27/04

    CPC classification number: H04L27/361 ,  H04B1/0475 ,  H04B1/0483

    Abstract: The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed.

    Abstract translation: 所公开的极性调制发射机电路被配置为产生具有最小化不同传输频带（例如，蓝牙，GSM，UMTS等）之间的串扰效应的传输频率的输出信号。 特别地，具有幅度调制（AM）信号和相位调制（PM）信号的极性调制收发器电路包括被配置为产生具有DCO频率的DCO信号的数字控制振荡器（DCO）。 DCO信号被提供给一个或多个分频器，其被配置为选择性地划分DCO信号以产生各种较低频率信号，用于选择在AM信号上操作的DAC的采样率和RF载波信号频率，其结果 在具有不干扰同一IC上的其它RF系统的频率的输出信号（例如，其落在其他RF系统的下行链路频率之外）。 还公开了其它系统和方法。

    Circuit with noise shaper
    10.
    发明申请
    Circuit with noise shaper 有权
    电路与噪音整形器

    公开(公告)号：US20100117743A1

    公开(公告)日：2010-05-13

    申请号：US12270584

    申请日：2008-11-13

    Applicant: Nicola Da Dalt ,  Edwin Thaller

    Inventor： Nicola Da Dalt ,  Edwin Thaller

    IPC: H03L7/08

    CPC classification number: H03L7/16 ,  H03L2207/50

    Abstract: In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping.

    Abstract translation: 在一个实施例中，提供了包括振荡器的电路。 基于反馈值和输入参考值来控制振荡器。 使用噪声整形产生反馈值或参考值或两者。

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