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    Digital circuit having delay circuit for adjustment of clock signal timing
    1.
    发明授权
    Digital circuit having delay circuit for adjustment of clock signal timing 有权
    具有用于调整时钟信号定时的延迟电路的数字电路

    公开(公告)号：US07274238B2

    公开(公告)日：2007-09-25

    申请号：US10520429

    申请日：2003-07-08

    Applicant: Eiichi Takahashi ,  Yuji Kasai ,  Tetsuya Higuchi

    Inventor： Eiichi Takahashi ,  Yuji Kasai ,  Tetsuya Higuchi

    IPC: H03H11/26

    CPC classification number: H03L7/07 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0805 ,  H03L7/0812

    Abstract: A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the pulse delay circuit has a stabilizing circuit for an amount of a pulse delay by a delay synchronizing loop, and a generating circuit for a pulse delay amount setting voltage with nonlinear characteristics. The present invention makes it possible to realize a timing delay circuit with high resolution, which is not influenced by an operating environment and requires only a small area for the circuit.

    Abstract translation: 根据本发明的数字电路包括脉冲延迟电路，其中逆变器的驱动电流是可变的，用于使时钟信号的定时可变; 并且脉冲延迟电路具有用于通过延迟同步环路的脉冲延迟量的稳定电路，以及具有非线性特性的脉冲延迟量设定电压的发生电路。 本发明使得可以实现不受操作环境影响的高分辨率的定时延迟电路，并且仅需要较小的电路面积。

    Digital circuit having a delay circuit for adjustment of clock signal timing
    3.
    发明申请
    Digital circuit having a delay circuit for adjustment of clock signal timing 有权
    具有用于调整时钟信号定时的延迟电路的数字电路

    公开(公告)号：US20060109146A1

    公开(公告)日：2006-05-25

    申请号：US10520429

    申请日：2003-07-08

    Applicant: Eiichi Takahashi ,  Yuji Kasai ,  Tetsuya Higuchi

    Inventor： Eiichi Takahashi ,  Yuji Kasai ,  Tetsuya Higuchi

    IPC: H03M7/00

    CPC classification number: H03L7/07 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0805 ,  H03L7/0812

    Abstract: A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the pulse delay circuit has a stabilizing circuit for an amount of a pulse delay by a delay synchronizing loop, and a generating circuit for a pulse delay amount setting voltage with nonlinear characteristics. The present invention makes it possible to realize a timing delay circuit with high resolution, which is not influenced by an operating environment and requires only a small area for the circuit.

    Abstract translation: 根据本发明的数字电路包括脉冲延迟电路，其中逆变器的驱动电流是可变的，用于使时钟信号的定时可变; 并且脉冲延迟电路具有用于通过延迟同步环路的脉冲延迟量的稳定电路，以及具有非线性特性的脉冲延迟量设定电压的发生电路。 本发明使得可以实现不受操作环境影响的高分辨率的定时延迟电路，并且仅需要较小的电路面积。

    SERIAL BUS TRANSMISSION SYSTEM
    4.
    发明申请
    SERIAL BUS TRANSMISSION SYSTEM 有权
    串行总线传输系统

    公开(公告)号：US20110142066A1

    公开(公告)日：2011-06-16

    申请号：US12988939

    申请日：2009-04-20

    Applicant: Yuji Kasai ,  Eiichi Takahashi ,  Masahiro Murakawa ,  Tetsuya Higuchi

    Inventor： Yuji Kasai ,  Eiichi Takahashi ,  Masahiro Murakawa ,  Tetsuya Higuchi

    IPC: H04B7/212

    CPC classification number: H04L12/4035

    Abstract: A master node (12) sends an identification signal for designating a communication channel in an identification signal time slot. When the own node matches the node in which the communication channel designated by the identification signal sent from the master node (12) is set in the identification signal time slot, the master node (12) and slave nodes (131 to 13n) each perform data transmission via the communication channel, based on the set contents of the communication channel, in the data transmission time slot corresponding to the identification signal time slot in which the identification signal has been sent.

    Abstract translation: 主节点（12）在识别信号时隙中发送用于指定通信信道的识别信号。 当自身节点与在主节点（12）发送的识别信号指定的通信信道被设置在识别信号时隙中的节点匹配时，主节点（12）和从节点（131至13n）各自执行 在与发送识别信号的识别信号时隙对应的数据传输时隙中，基于通信信道的设定内容，经由通信信道的数据传输。

    Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program
    5.
    发明授权
    Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program 失效
    信号定时调整装置，信号定时调整系统，信号定时调整量设定程序以及存储该程序的存储介质

    公开(公告)号：US07447289B2

    公开(公告)日：2008-11-04

    申请号：US10809374

    申请日：2004-03-26

    Applicant: Munehiro Uratani ,  Eiichi Takahashi ,  Yuji Kasai ,  Tetsuya Higuchi ,  Masahiro Murakawa

    Inventor： Munehiro Uratani ,  Eiichi Takahashi ,  Yuji Kasai ,  Tetsuya Higuchi ,  Masahiro Murakawa

    IPC: H04L7/00

    CPC classification number: H04L7/0337 ,  H03L7/087

    Abstract: Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.

    Abstract translation: 根据来自电路块的数据通过测量寄存器获取的定时和来自数据块的数据的定时，测量数据到电路块的数据输入与来自数据块的数据的输出之间的延迟时间 电路块由数据锁存器获取。 LSI测试仪设置好的电压调整值，使得每个电路块的延迟时间被平均。 根据由调整电压产生电路产生的电压，选择器选择与电压调节值相一致的电压。 所选择的电压被施加到每个时钟定时调整电路的CMOS晶体管的阱。 因此调整输入时钟的定时之间的延迟时间。

    Bus driver with well voltage control section
    6.
    发明授权
    Bus driver with well voltage control section 失效
    总线驱动器与井电压控制部分

    公开(公告)号：US07248095B2

    公开(公告)日：2007-07-24

    申请号：US11213779

    申请日：2005-08-30

    Applicant: Munehiro Uratani ,  Yuji Kasai ,  Tetsuya Higuchi ,  Eiichi Takahashi

    Inventor： Munehiro Uratani ,  Yuji Kasai ,  Tetsuya Higuchi ,  Eiichi Takahashi

    IPC: G05F1/10

    CPC classification number: H03K19/0005 ,  H03K19/018557

    Abstract: A bus driving device is provided with a driver circuit for driving a bus line thereof. The driver circuit includes an MOS transistor whose well is separated from other circuits. Further, the bus driving device is provided with a voltage control section for adjusting a well voltage, in accordance with a level of a signal in the bus line. With this bus driving device, a threshold voltage of the MOS transistor is set at a predetermined target value.

    Abstract translation: 总线驱动装置设有用于驱动总线的驱动电路。 驱动电路包括一个与其他电路分离的MOS晶体管。 此外，总线驱动装置设置有用于根据总线中的信号的电平来调节阱电压的电压控制部。 利用该总线驱动装置，将MOS晶体管的阈值电压设定为规定的目标值。

    Digital system, clock signal adjusting method for digital system, recording medium recording processing program executed in the adjusting method
    8.
    发明申请
    Digital system, clock signal adjusting method for digital system, recording medium recording processing program executed in the adjusting method 审中-公开
    数字系统，数字系统的时钟信号调整方法，以调整方式执行的记录介质记录处理程序

    公开(公告)号：US20060236146A1

    公开(公告)日：2006-10-19

    申请号：US10559672

    申请日：2004-06-03

    Applicant: Eiichi Takahashi ,  Masahiro Murakawa ,  Yuji Kasai ,  Tetsuya Higuchi

    Inventor： Eiichi Takahashi ,  Masahiro Murakawa ,  Yuji Kasai ,  Tetsuya Higuchi

    IPC: G06F1/12

    CPC classification number: G06F1/10 ,  G01R31/31725 ,  G01R31/31726 ,  H03K2005/00058 ,  H03K2005/00156 ,  H03K2005/0026

    Abstract: A digital system (1) which performs a digital processing according to a single or a plurality of clock signals to deliver a specified basic function, and which comprises a plurality of delay elements (4) respectively inserted into a plurality of clock circuits for supplying clock signals in a digital system, and respectively constituted by circuit elements for changing delay times according to values indicated by a control signal, and a plurality of holding circuits (5) for holding a plurality of control signals to be given to a plurality of delay elements. The plurality of holding circuits have a plurality of control signal values, held by these holding circuits, changed by external devices (6-8) according to a probabilistic search method with the digital system (1) supplied with power from a variable-output-voltage power supply (14) so that the basic function of the digital system satisfies specified specifications.

    Abstract translation: 一种数字系统（1），其根据单个或多个时钟信号执行数字处理以传送指定的基本功能，并且包括分别插入到多个时钟电路中的多个延迟元件（4），用于提供时钟 信号，并且分别由用于根据控制信号指示的值改变延迟时间的电路元件构成，以及多个保持电路（5），用于保持多个控制信号被提供给多个延迟元件 。 多个保持电路具有由这些保持电路保持的多个控制信号值，根据概率搜索方法由外部设备（6-8）改变，数字系统（1）从可变输出 - 电压电源（14），使数字系统的基本功能满足规定的规格。

    Bus driver and semiconductor integrated circuit
    9.
    发明申请
    Bus driver and semiconductor integrated circuit 失效
    总线驱动器和半导体集成电路

    公开(公告)号：US20060055449A1

    公开(公告)日：2006-03-16

    申请号：US11213779

    申请日：2005-08-30

    Applicant: Munehiro Uratani ,  Yuji Kasai ,  Tetsuya Higuchi ,  Eiichi Takahashi

    Inventor： Munehiro Uratani ,  Yuji Kasai ,  Tetsuya Higuchi ,  Eiichi Takahashi

    IPC: H03K3/01

    CPC classification number: H03K19/0005 ,  H03K19/018557

    Abstract: A bus driving device is provided with a driver circuit for driving a bus line thereof. The driver circuit includes an MOS transistor whose well is separated from other circuits. Further, the bus driving device is provided with a voltage control section for adjusting a well voltage, in accordance with a level of a signal in the bus line. With this bus driving device, a threshold voltage of the MOS transistor is set at a predetermined target value.

    Abstract translation: 总线驱动装置设有用于驱动总线的驱动电路。 驱动电路包括一个与其他电路分离的MOS晶体管。 此外，总线驱动装置设置有用于根据总线中的信号的电平来调节阱电压的电压控制部。 利用该总线驱动装置，将MOS晶体管的阈值电压设定为规定的目标值。

    Serial bus transmission system
    10.
    发明授权
    Serial bus transmission system 有权
    串行总线传输系统

    公开(公告)号：US08493991B2

    公开(公告)日：2013-07-23

    申请号：US12988939

    申请日：2009-04-20

    Applicant: Yuji Kasai ,  Eiichi Takahashi ,  Masahiro Murakawa ,  Tetsuya Higuchi

    Inventor： Yuji Kasai ,  Eiichi Takahashi ,  Masahiro Murakawa ,  Tetsuya Higuchi

    IPC: H04B7/212 ,  H04B1/44 ,  H04Q11/00 ,  H04J3/00 ,  H04L12/40 ,  H04L7/00 ,  H04W4/00

    CPC classification number: H04L12/4035

    Abstract: A master node (12) sends an identification signal for designating a communication channel in an identification signal time slot. When the own node matches the node in which the communication channel designated by the identification signal sent from the master node (12) is set in the identification signal time slot, the master node (12) and slave nodes (131 to 13n) each perform data transmission via the communication channel, based on the set contents of the communication channel, in the data transmission time slot corresponding to the identification signal time slot in which the identification signal has been sent.

    Abstract translation: 主节点（12）在识别信号时隙中发送用于指定通信信道的识别信号。 当自身节点与在主节点（12）发送的识别信号指定的通信信道被设置在识别信号时隙中的节点匹配时，主节点（12）和从节点（131至13n）各自执行 在与发送识别信号的识别信号时隙对应的数据传输时隙中，基于通信信道的设定内容，经由通信信道的数据传输。

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