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11 条记录 (耗时 0.023 秒)

    Method of forming a trench with a rounded bottom in a semiconductor device
    1.
    发明授权
    Method of forming a trench with a rounded bottom in a semiconductor device 有权
    在半导体器件中形成具有圆形底部的沟槽的方法

    公开(公告)号：US06521538B2

    公开(公告)日：2003-02-18

    申请号：US09790888

    申请日：2001-02-23

    申请人： Hajime Soga ,  Kenji Kondo ,  Eiji Ishikawa ,  Yoshikazu Sakano ,  Mikimasa Suzuki

    发明人： Hajime Soga ,  Kenji Kondo ,  Eiji Ishikawa ,  Yoshikazu Sakano ,  Mikimasa Suzuki

    IPC分类号： H01L21311

    CPC分类号： H01L29/7813 ,  H01L21/76232 ,  H01L21/763 ,  H01L29/4236 ,  H01L29/66348

    摘要： In a method for manufacturing a semiconductor device, first, a trench is formed on a semiconductor substrate by anisotropic etching, and a reaction product is produced and deposited on the inner wall of the trench during the anisotropic etching. Then, isotropic etching is performed to round a corner of a bottom portion of the trench without removing the reaction product. The isotropic etching can round the corner of the trench without etching the side wall of the trench that is covered by the reaction product.

    摘要翻译： 在制造半导体器件的方法中，首先，通过各向异性蚀刻在半导体衬底上形成沟槽，并且在各向异性蚀刻期间，在沟槽的内壁上产生并沉积反应产物。 然后，进行各向同性蚀刻，以在沟槽的底部的一个角部周围，而不去除反应产物。 各向同性蚀刻可以围绕沟槽的角落，而不蚀刻由反应产物覆盖的沟槽的侧壁。

    Integrated gate bipolar transistor and method of manufacturing the same
    2.
    发明授权
    Integrated gate bipolar transistor and method of manufacturing the same 有权
    集成门双极晶体管及其制造方法

    公开(公告)号：US06482701B1

    公开(公告)日：2002-11-19

    申请号：US09630786

    申请日：2000-08-02

    申请人： Eiji Ishikawa ,  Kenji Kondo ,  Hajime Soga

    发明人： Eiji Ishikawa ,  Kenji Kondo ,  Hajime Soga

    IPC分类号： H01L21336

    CPC分类号： H01L29/66348 ,  H01L21/3065

    摘要： A method of manufacturing a trench gate type IGBT element, which can sufficiently round off a corner at a bottom of a trench with restricting silicon from being excessively etched. A trench is formed at a surface of a P+-type monocrystalline silicon substrate by conducting an anisotropic etching (STEP 1). A corner portion at a bottom of the trench is formed to a concave shape surface by conducting a concave etching (STEP 2). The concave etching etches the silicon substrate so that a diameter of the trench is gradually reduced as the etching advances. After that, the corner portion at a bottom of the trench is rounded off by conducting an isotropic etching (STEP 3). Since the corner portion is chamfered, a radius of curvature of the corner portion of the bottom of the trench can be increased even if an amount of the etching using the isotropic etching in the STEP 3 is small.

    摘要翻译： 一种制造沟槽栅型IGBT元件的方法，其可以使沟槽的底部的拐角充分地圆形化，从而限制硅的过度蚀刻。 通过进行各向异性蚀刻在P +型单晶硅衬底的表面上形成沟槽（步骤1）。 通过进行凹蚀刻将沟槽底部的角部形成为凹形表面（步骤2）。 凹蚀刻蚀刻硅衬底，使得随着蚀刻的进行，沟槽的直径逐渐减小。 之后，通过进行各向同性蚀刻使沟槽底部的角部被倒圆（步骤3）。 由于角部被倒角，即使在步骤3中使用各向同性蚀刻的蚀刻量少的情况下，沟槽底部的角部的曲率半径也可以增加。

    Dry etching method for semiconductor substrate
    3.
    发明授权
    Dry etching method for semiconductor substrate 失效
    半导体衬底的干蚀刻方法

    公开(公告)号：US6090718A

    公开(公告)日：2000-07-18

    申请号：US992108

    申请日：1997-12-17

    申请人： Hajime Soga ,  Kenji Kondo ,  Eiji Ishikawa ,  Yoshikazu Sakano ,  Yuji Ichikawa

    发明人： Hajime Soga ,  Kenji Kondo ,  Eiji Ishikawa ,  Yoshikazu Sakano ,  Yuji Ichikawa

    IPC分类号： C23F4/00 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  H01H21/302

    CPC分类号： H01L21/67069 ,  Y10S438/905 ,  Y10S438/906

    摘要： After performing an etching process with respect to one substrate, the substrate is taken out from an etching chamber. Then, a dummy substrate is disposed in the etching chamber and a cleaning process is performed. The cleaning process includes a cleaning step for etching reaction products produced during the etching process to be removed, a seasoning step for adjusting the atmosphere within the etching chamber and the temperature of the substrate, and a purge step for removing suspended foreign materials without generating plasma. By performing the cleaning process, the successive etching process can be performed without generating any black silicon on the substrate, thereby attaining a high production yield.

    摘要翻译： 在对一个基板进行蚀刻处理之后，从蚀刻室取出基板。 然后，在蚀刻室内设置虚设基板，进行清洗处理。 清洗过程包括用于蚀刻在要除去的蚀刻工艺期间产生的反应产物的清洁步骤，用于调节蚀刻室内的气氛的调节步骤和基板的温度，以及用于清除悬浮的异物而不产生等离子体的吹扫步骤 。 通过进行清洗处理，可以在基板上不产生任何黑色硅的情况下进行连续蚀刻处理，从而获得高产率。

    Dry etching process for semiconductor
    4.
    发明授权
    Dry etching process for semiconductor 失效
    半导体干蚀刻工艺

    公开(公告)号：US5871659A

    公开(公告)日：1999-02-16

    申请号：US665545

    申请日：1996-06-18

    申请人： Yoshikazu Sakano ,  Kenji Kondo ,  Hajime Soga ,  Yasuo Ishihara ,  Yoshifumi Okabe

    发明人： Yoshikazu Sakano ,  Kenji Kondo ,  Hajime Soga ,  Yasuo Ishihara ,  Yoshifumi Okabe

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  B44C1/22

    CPC分类号： H01L21/3065

    摘要： A process for dry etching a silicon substrate, in which a mask exposing a region of the surface of the silicon substrate is formed, and the exposed region is dry etched. The dry etching is performed with a gas mixture including chlorine or a chlorine-containing gas, an oxygen-containing gas, and a fluorine-containing gas in which a ratio of a flow rate of oxygen gas to a flow rate of chlorine gas, O.sub.2 /Cl.sub.2, is selected to be from 0.6 to 3. The gas mixture may also contain a fluorine-containing gas and helium. Preferably, the gas mixture excludes carbon-containing gases. The dry etching process allows for an increased etch rate, as well as a high etch selectivity compared to that of SiO.sub.2 gas. The trench formed in the substrate by this process can be made of a larger depth with high reproducibility and good configuration. The sidewall profile angle of the trench is maintained slightly tapered, with a sidewall profile angle of approximately 90 degrees. Also, by mixing HBr gas into the gas mixture, it is possible to better control the formation of the trench. Thus, this process makes it possible to form, in a silicon substrate, a regularly configured and very deep trench with high accuracy and high etch rate.

    摘要翻译： 一种用于干蚀刻硅衬底的方法，其中形成露出硅衬底表面的区域的掩模，并且暴露区域被干蚀刻。 干蚀刻用包括氯或含氯气体，含氧气体和含氟气体的气体混合物进行，其中氧气流量与氯气流量的比例为O 2 / Cl2被选择为0.6至3.气体混合物还可含有含氟气体和氦气。 优选地，气体混合物不包括含碳气体。 与SiO 2气体相比，干蚀刻工艺允许提高蚀刻速率，以及高蚀刻选择性。 通过该工艺在衬底中形成的沟槽可以由更大的深度制成，具有高的再现性和良好的配置。 沟槽的侧壁轮廓角保持略微渐缩，侧壁轮廓角度约为90度。 此外，通过将HBr气体混入气体混合物中，可以更好地控制沟槽的形成。 因此，该方法使得可以在硅衬底中形成具有高精度和高蚀刻速率的规则构造和非常深的沟槽。

    Method of producing a thin film resistor
    5.
    发明授权
    Method of producing a thin film resistor 有权
    制造薄膜电阻的方法

    公开(公告)号：US6165862A

    公开(公告)日：2000-12-26

    申请号：US143514

    申请日：1998-08-28

    申请人： Eizi Ishikawa ,  Kenji Kondo ,  Hajime Soga

    发明人： Eizi Ishikawa ,  Kenji Kondo ,  Hajime Soga

    IPC分类号： H01L21/02 ,  H01L21/20

    CPC分类号： H01L28/24

    摘要： After a CrSiN film and a TiW film are formed on a substrate through an intermediate insulating layer, a mask pattern is formed on the TiW film. Then a two-step dry etching treatment is performed to etch the TiW film and the CrSiN film into a specific shape. Specifically, first the TiW film is selectively etched under conditions including a large content of fluorine radicals. Then the CrSiN film is selectively etched under conditions including a large content of oxygen radicals. Accordingly, a thin film resistor can be formed with high accuracy with respect to the mask pattern.

    摘要翻译： 在通过中间绝缘层在基板上形成CrSiN膜和TiW膜之后，在TiW膜上形成掩模图案。 然后进行两步干蚀刻处理以将TiW膜和CrSiN膜蚀刻成特定形状。 具体地说，首先在包含大量氟自由基的条件下选择性地蚀刻TiW膜。 然后在包括大量氧自由基的条件下选择性地蚀刻CrSiN膜。 因此，可以相对于掩模图案高精度地形成薄膜电阻器。

    Semiconductor device and method for manufacturing the same
    6.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06469345B2

    公开(公告)日：2002-10-22

    申请号：US09758377

    申请日：2001-01-12

    申请人： Takaaki Aoki ,  Yutaka Tomatsu ,  Akira Kuroyanagi ,  Mikimasa Suzuki ,  Hajime Soga

    发明人： Takaaki Aoki ,  Yutaka Tomatsu ,  Akira Kuroyanagi ,  Mikimasa Suzuki ,  Hajime Soga

    IPC分类号： H01L2976

    CPC分类号： H01L29/7813 ,  H01L21/28202 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/7397

    摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film is composed of a first portion disposed on a side wall portion of the trench and a second portion disposed on upper and bottom portions of the trench. The first portion is composed of a first oxide film, a nitride film, and a second oxide film. The second portion is composed of only an oxide film and has a thickness thicker than that of the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be mitigated, and a decrease in withstand voltage at that portions can be prevented.

    摘要翻译： 沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。 栅极绝缘膜由设置在沟槽的侧壁部分上的第一部分和设置在沟槽的上部和底部的第二部分组成。 第一部分由第一氧化物膜，氮化物膜和第二氧化物膜组成。 第二部分仅由氧化膜构成，其厚度比第一部分厚。 因此，可以减轻沟槽上下角部的电场集中，能够防止该部分的耐电压降低。

    Heterojunction magnetic field sensor
    7.
    发明授权
    Heterojunction magnetic field sensor 失效
    异质结磁场传感器

    公开(公告)号：US4912451A

    公开(公告)日：1990-03-27

    申请号：US291649

    申请日：1988-12-29

    申请人： Yoshinobu Sugiyama ,  Munecazu Tacano ,  Hajime Soga

    发明人： Yoshinobu Sugiyama ,  Munecazu Tacano ,  Hajime Soga

    IPC分类号： H01L43/06

    CPC分类号： H01L43/065

    摘要： The heterojunction magnetic field sensor is basically a heterojunction structure forming a two-dimensional electron gas layer having a high carrier mobility at the junction portion of at least two different kinds of semiconductor layers having a different band gap, respectively, and further, at least one semiconductor layer having a quantum well structure is provided adjacent to and in contact with the two dimensional electron gas layer, the energy level of the ground state subband thereof being higher than that of the two-dimensional electron gas layer. This heterojunction magnetic field sensor has a high sensitivity which is not saturated even under a high electric field and provides an enhanced output even under the high electric field.

    摘要翻译： 异质结磁场传感器基本上是异相结构，其分别在具有不同带隙的至少两种不同种类的半导体层的接合部分分别形成具有高载流子迁移率的二维电子气体层，此外，至少一个 提供与二维电子气层相邻并与之接触的具有量子阱结构的半导体层，其基态子带的能级高于二维电子气层的能级。 该异质结磁场传感器具有高灵敏度，即使在高电场下也不饱和，甚至在高电场下也能提供增强的输出。

    Semiconductor device having multilayer interconnection structure and method for manufacturing the same
    9.
    发明授权
    Semiconductor device having multilayer interconnection structure and method for manufacturing the same 失效
    具有多层互连结构的半导体装置及其制造方法

    公开(公告)号：US06274452B1

    公开(公告)日：2001-08-14

    申请号：US08965030

    申请日：1997-11-05

    申请人： Shoji Miura ,  Satoshi Shiraki ,  Hajime Soga

    发明人： Shoji Miura ,  Satoshi Shiraki ,  Hajime Soga

    IPC分类号： H01L2120

    CPC分类号： H01L28/20 ,  H01L21/84 ,  H01L27/13 ,  H01L2924/0002 ,  H01L2924/00

    摘要： After an insulating layer made of BPSG is formed on a diffusion layer, a contact hole is formed to expose the diffusion layer. Then, a first aluminum layer is formed in the contact hole. Then, first and second TEOS layers are formed. Thereafter, a thin film resistor is formed on the second TEOS layer by photo-lithography and etching treatments. In this process, the other parts are covered with the second TEOS layer to prevent being damaged. As a result, occurrence of a leak current at the diffusion layer and the like can be prevented. Further, a third TEOS layer is formed on the thin film resistor, and then a second aluminum layer is formed to be electrically connected to the thin film resistor through a contact hole by an ECR dry etching treatment. In this etching treatment, the thin film resistor is not damaged due to the third TEOS layer.

    摘要翻译： 在扩散层上形成由BPSG制成的绝缘层之后，形成接触孔以露出扩散层。 然后，在接触孔中形成第一铝层。 然后，形成第一和第二TEOS层。 此后，通过光刻和蚀刻处理在第二TEOS层上形成薄膜电阻器。 在此过程中，其他部分被第二个TEOS层覆盖，以防止损坏。 结果，可以防止在扩散层等处发生泄漏电流。 此外，在薄膜电阻器上形成第三TEOS层，然后通过ECR干蚀刻处理通过接触孔形成第二铝层与薄膜电阻器电连接。 在这种蚀刻处理中，由于第三TEOS层，薄膜电阻器不会被损坏。