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17 条记录 (耗时 0.026 秒)

    Semiconductor device and method for manufacturing the same
    1.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06469345B2

    公开(公告)日：2002-10-22

    申请号：US09758377

    申请日：2001-01-12

    申请人： Takaaki Aoki ,  Yutaka Tomatsu ,  Akira Kuroyanagi ,  Mikimasa Suzuki ,  Hajime Soga

    发明人： Takaaki Aoki ,  Yutaka Tomatsu ,  Akira Kuroyanagi ,  Mikimasa Suzuki ,  Hajime Soga

    IPC分类号： H01L2976

    CPC分类号： H01L29/7813 ,  H01L21/28202 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/7397

    摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film is composed of a first portion disposed on a side wall portion of the trench and a second portion disposed on upper and bottom portions of the trench. The first portion is composed of a first oxide film, a nitride film, and a second oxide film. The second portion is composed of only an oxide film and has a thickness thicker than that of the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be mitigated, and a decrease in withstand voltage at that portions can be prevented.

    摘要翻译： 沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。 栅极绝缘膜由设置在沟槽的侧壁部分上的第一部分和设置在沟槽的上部和底部的第二部分组成。 第一部分由第一氧化物膜，氮化物膜和第二氧化物膜组成。 第二部分仅由氧化膜构成，其厚度比第一部分厚。 因此，可以减轻沟槽上下角部的电场集中，能够防止该部分的耐电压降低。

    Vertical type semiconductor device and gate structure
    5.
    发明授权
    Vertical type semiconductor device and gate structure 失效
    垂直型半导体器件和栅极结构

    公开(公告)号：US5798550A

    公开(公告)日：1998-08-25

    申请号：US469622

    申请日：1995-06-06

    申请人： Akira Kuroyanagi ,  Masami Yamaoka ,  Yoshifumi Okabe ,  Yasuaki Tsuzuki ,  Yutaka Tomatsu

    发明人： Akira Kuroyanagi ,  Masami Yamaoka ,  Yoshifumi Okabe ,  Yasuaki Tsuzuki ,  Yutaka Tomatsu

    IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/66719 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/7811 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/1095

    摘要： The present invention involves a vertical type semiconductor device whereby miniaturization and lowered ON resistance of a cell within the device can be achieved without impairing the functioning of the device. The line width of the gate electrode is made smaller to meeting the demand for miniaturization of the cell while the distance between the channel regions which are diffused into the portions below the gate during double diffusion remains virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. While the width of the gate electrode is set to be smaller, the mask members used during double diffusion are attached to the side walls of the gate electrode, where their width allows the source region to diffuse to the portion under the gate. Accordingly, miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.

    摘要翻译： 本发明涉及垂直型半导体器件，由此可以实现器件内的电池的小型化和降低的导通电阻，而不会损害器件的功能。 使栅电极的线宽变小以满足电池小型化的需要，而在双扩散期间扩散到栅极下方的沟道区域之间的距离实际上等于在较大单元尺寸的器件中的沟道区域之间的距离 具有低JFET电阻分量。 虽然栅电极的宽度设定得较小，但是在双扩散期间使用的掩模构件附接到栅电极的侧壁，其宽度允许源极区域扩散到栅极下方的部分。 因此，可以实现电池的小型化和降低的导通电阻，而不会损害器件的功能。

    Method for producing semiconductor device having DMOS and NMOS elements formed in the same substrate
    6.
    发明授权
    Method for producing semiconductor device having DMOS and NMOS elements formed in the same substrate 失效
    用于制造具有形成在同一衬底中的DMOS和NMOS元件的半导体器件的方法

    公开(公告)号：US5550067A

    公开(公告)日：1996-08-27

    申请号：US38953

    申请日：1993-03-29

    申请人： Akira Kuroyanagi ,  Yutaka Tomatsu ,  Yasuaki Tsuzuki

    发明人： Akira Kuroyanagi ,  Yutaka Tomatsu ,  Yasuaki Tsuzuki

    IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8236 ,  H01L29/06 ,  H01L29/78 ,  H01L21/265

    CPC分类号： H01L29/66712 ,  H01L21/823456 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/1095 ,  H01L29/402

    摘要： An intelligent power element has integrated DMOS transistors and control elements such as NMOS transistors. Impurity concentration inside a channel well (4) of each DMOS transistor is denser than that at the surface thereof. This results in reducing the reach-through withstand voltage of the DMOS transistor to less than that of the NMOS transistor. As a result, a reach-through phenomenon occurs on the DMOS transistor having a higher allowable (withstand) current before it occurs on the NMOS transistor having a lower allowable current. To provide the same effect, the reach-through withstand voltage of the DMOS transistor may be decreased by forming an internal high concentration well (201) at an upper part of a deep main well (31) of the DMOS transistor. The well (201) is shallower than the main well (31) and does not extend under a gate electrode (71).

    摘要翻译： 智能功率元件集成了DMOS晶体管和诸如NMOS晶体管的控制元件。 每个DMOS晶体管的通道阱（4）内的杂质浓度比其表面处的浓度更致密。 这导致将DMOS晶体管的可达耐受电压降低到小于NMOS晶体管的耐受电压。 结果，在具有较低可允许电流的NMOS晶体管上发生之前，在具有较高允许（耐受）电流的DMOS晶体管上会发生到达现象现象。 为了提供相同的效果，可以通过在DMOS晶体管的深主阱（31）的上部形成内部高浓度阱（201）来降低DMOS晶体管的到达耐受电压。 井（201）比主井（31）浅，并且不在栅电极（71）下延伸。

    Manufacturing method of semiconductor device with a groove
    7.
    发明授权
    Manufacturing method of semiconductor device with a groove 失效
    具有凹槽的半导体器件的制造方法

    公开(公告)号：US5998268A

    公开(公告)日：1999-12-07

    申请号：US938472

    申请日：1997-09-29

    申请人： Yutaka Tomatsu ,  Takeshi Miyajima ,  Manabu Koike ,  Ryosuke Inoshita

    发明人： Yutaka Tomatsu ,  Takeshi Miyajima ,  Manabu Koike ,  Ryosuke Inoshita

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

    CPC分类号： H01L29/7397 ,  H01L29/66348 ,  H01L29/1095

    摘要： On the surface of a semiconductor substrate there are formed a silicon oxide film, silicon nitride film and resist, whereby a groove is formed in the semiconductor substrate through an opening portion by chemical dry etching. An oxide film is formed on the inner surface of the groove by wet oxidation and, further, this oxide film is removed by wet etching, after which the surface of the semiconductor substrate located on the outer-peripheral side of the groove from an angular portion defined between a side surface of the groove and the surface of the semiconductor substrate is exposed. Then, the inner surface of the groove and the exposed surface of the semiconductor substrate are oxidized to thereby form a LOCOS oxide film, and thereafter this LOCOS oxide film is removed. As a result of this, the angular portion is made round, thereby enabling the avoidance of the concentration of an electric field on the angular portion of the groove.

    摘要翻译： 在半导体衬底的表面上形成氧化硅膜，氮化硅膜和抗蚀剂，由此通过化学干蚀刻通过开口部分在半导体衬底中形成沟槽。 通过湿式氧化在沟槽的内表面上形成氧化膜，此外，通过湿蚀刻除去该氧化物膜，然后从位于槽的外周侧的半导体衬底的表面从角部 限定在凹槽的侧表面和半导体衬底的表面之间。 然后，将沟槽的内表面和半导体衬底的暴露表面氧化，从而形成LOCOS氧化物膜，然后除去该LOCOS氧化物膜。 其结果是，角部形成为圆形，从而能够避免沟槽的角部上的电场集中。

    Semiconductor device and method of producing the same
    8.
    发明授权
    Semiconductor device and method of producing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US5877527A

    公开(公告)日：1999-03-02

    申请号：US847599

    申请日：1997-04-25

    申请人： Yoshifumi Okabe ,  Mitsuhiro Kataoka ,  Yutaka Tomatsu

    发明人： Yoshifumi Okabe ,  Mitsuhiro Kataoka ,  Yutaka Tomatsu

    IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L29/792

    CPC分类号： H01L29/7813 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/0847

    摘要： In a semiconductor device having a substrate, a p-type semiconductor layer, an n-type channel well region, a p-type lightly doped source region, and a source electrode formed on the substrate in this order, a p-type heavily-doped source region, an impurity concentration of which is higher than that of the lightly-doped source region, is formed in a surface region of the lightly-doped source region. The source electrode is formed to contact the heavily-doped source region. As a result, a punch through phenomenon between the p-type source region and the p-type semiconductor layer through the n-type channel well region can be prevented without increasing in the On resistance of the semiconductor device.

    摘要翻译： 在具有衬底，p型半导体层，n型沟道阱区，p型轻掺杂源极区域和在该衬底上形成的源极电极的半导体器件中， 在轻掺杂源极区域的表面区域中形成杂质浓度高于轻掺杂源极区域的掺杂源极区域。 源电极形成为接触重掺杂源极区。 结果，可以在不增加半导体器件的导通电阻的情况下，防止通过n型沟道阱区域的p型源极区域和p型半导体层之间的穿透现象。