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公开(公告)号：US08969169B1
公开(公告)日：2015-03-03
申请号：US14033326
申请日：2013-09-20
CPC分类号： H01L28/56 , H01L27/108 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/82
摘要： A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.
摘要翻译： 形成电容器堆叠的方法包括形成包括导电金属氮化物材料的第一底部电极层。 在第一底部电极层的上方形成第二底部电极层。 第二底部电极层包括导电金属氧化物材料，其中导电金属氧化物材料的晶体结构促进随后沉积的介电层的期望的高k结晶相。 在第二底部电极层的上方形成电介质层。 任选地，在介电层上方形成富氧金属氧化物层。 可选地，在富氧金属氧化物层的上方形成第三上电极层。 第三顶部电极层包括导电金属氧化物材料。 第四上电极层形成在第三顶电极层的上方。 第四顶部电极层包括导电金属氮化物材料。
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公开(公告)号：US09281357B2
公开(公告)日：2016-03-08
申请号：US14599843
申请日：2015-01-19
IPC分类号： H01L49/02 , H01L27/108
CPC分类号： H01L28/56 , H01L27/108 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/82
摘要： A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.
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公开(公告)号：US20150137315A1
公开(公告)日：2015-05-21
申请号：US14599843
申请日：2015-01-19
IPC分类号： H01L49/02 , H01L27/108
CPC分类号： H01L28/56 , H01L27/108 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/82
摘要： A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.
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公开(公告)号：US20150087130A1
公开(公告)日：2015-03-26
申请号：US14033326
申请日：2013-09-20
IPC分类号： H01L49/02
CPC分类号： H01L28/56 , H01L27/108 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/82
摘要： A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.
摘要翻译： 形成电容器堆叠的方法包括形成包括导电金属氮化物材料的第一底部电极层。 在第一底部电极层的上方形成第二底部电极层。 第二底部电极层包括导电金属氧化物材料，其中导电金属氧化物材料的晶体结构促进随后沉积的介电层的期望的高k结晶相。 在第二底部电极层的上方形成电介质层。 任选地，在介电层上方形成富氧金属氧化物层。 可选地，在富氧金属氧化物层的上方形成第三上电极层。 第三顶部电极层包括导电金属氧化物材料。 第四上电极层形成在第三顶电极层的上方。 第四顶部电极层包括导电金属氮化物材料。
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5.发明授权Method of forming anneal-resistant embedded resistor for non-volatile memory application 有权用于非易失性存储器应用的形成耐退火嵌入式电阻器的方法公开(公告)号：US08981329B1
公开(公告)日：2015-03-17
申请号：US14548408
申请日：2014-11-20
发明人： Mihir Tendulkar , David Chi
CPC分类号： H01L45/146 , H01L21/28506 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L28/24 , H01L45/06 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/1616 , H01L45/1641
摘要： Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.
摘要翻译： 本发明的实施例包括具有改进的器件性能和寿命的非易失性电阻随机存取存储器件的非易失性存储器件。 在一些实施例中，非易失性电阻随机存取存储器件包括二极管，金属氮化硅嵌入式电阻器和设置在第一电极层和第二电极层之间的电阻开关层。 在一些实施例中，形成电阻随机存取存储器件的方法包括形成二极管，形成金属氮化硅嵌入式电阻器，形成第一电极层，形成第二电极层，以及形成电阻开关层， 层和第二电极层。
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6.发明申请公开(公告)号：US20140124725A1
公开(公告)日：2014-05-08
申请号：US13671824
申请日：2012-11-08
申请人： INTERMOLECULAR, INC.
发明人： David Chi , Vidyut Gopal , Minh Huu Le , Minh Anh Nguyen , Dipankar Pramanik , Milind Weling
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , G11C13/0007 , G11C2213/32 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/14 , H01L45/146 , H01L45/1616
摘要： Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from doped metal oxides and/or nitrides. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature annealing. In some embodiments, the breakdown voltage of a current limiting layer may be at least about 8V. Some examples of such current limiting layers include titanium oxide doped with niobium, tin oxide doped with antimony, and zinc oxide doped with aluminum. Dopants and base materials may be deposited as separate sub-layers and then redistributed by annealing or may be co-deposited using reactive sputtering or co-sputtering. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layer while maintaining their performance.
摘要翻译： 提供了诸如电阻随机存取存储器（ReRAM）单元的半导体器件，其包括由掺杂的金属氧化物和/或氮化物形成的限流层。 这些限流层可具有至少约1欧姆 - 厘米的电阻率。 即使当这些层受到强电场和/或高温退火时，也保持该电阻率水平。 在一些实施例中，限流层的击穿电压可以为至少约8V。 这种电流限制层的一些实例包括掺杂有铌的氧化钛，掺杂有锑的氧化锡和掺杂有铝的氧化锌。 掺杂剂和基材可以作为单独的子层沉积，然后通过退火重新分布，或者可以使用反应溅射或共溅射共沉积。 层的高电阻率允许在保持其性能的同时缩小包括这些层的半导体器件的尺寸。
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公开(公告)号：US20150069319A1
公开(公告)日：2015-03-12
申请号：US14548408
申请日：2014-11-20
发明人： Mihir Tendulkar , David Chi
CPC分类号： H01L45/146 , H01L21/28506 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L28/24 , H01L45/06 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/1616 , H01L45/1641
摘要： Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.
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8.发明授权公开(公告)号：US08912518B2
公开(公告)日：2014-12-16
申请号：US13671824
申请日：2012-11-08
申请人： Intermolecular, Inc.
发明人： David Chi , Vidyut Gopal , Minh Huu Le , Minh Anh Nguyen , Dipankar Pramanik , Milind Weling
CPC分类号： H01L45/145 , G11C13/0007 , G11C2213/32 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/14 , H01L45/146 , H01L45/1616
摘要： Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from doped metal oxides and/or nitrides. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature annealing. In some embodiments, the breakdown voltage of a current limiting layer may be at least about 8V. Some examples of such current limiting layers include titanium oxide doped with niobium, tin oxide doped with antimony, and zinc oxide doped with aluminum. Dopants and base materials may be deposited as separate sub-layers and then redistributed by annealing or may be co-deposited using reactive sputtering or co-sputtering. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layer while maintaining their performance.
摘要翻译： 提供了诸如电阻随机存取存储器（ReRAM）单元的半导体器件，其包括由掺杂的金属氧化物和/或氮化物形成的限流层。 这些限流层可具有至少约1欧姆 - 厘米的电阻率。 即使当这些层受到强电场和/或高温退火时，也保持该电阻率水平。 在一些实施例中，限流层的击穿电压可以为至少约8V。 这种电流限制层的一些实例包括掺杂有铌的氧化钛，掺杂有锑的氧化锡和掺杂有铝的氧化锌。 掺杂剂和基材可以作为单独的子层沉积，然后通过退火重新分布，或者可以使用反应溅射或共溅射共沉积。 层的高电阻率允许在保持其性能的同时缩小包括这些层的半导体器件的尺寸。
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9.发明授权Method of forming anneal-resistant embedded resistor for non-volatile memory application 有权用于非易失性存储器应用的形成耐退火嵌入式电阻器的方法公开(公告)号：US08921154B1
公开(公告)日：2014-12-30
申请号：US14468687
申请日：2014-08-26
发明人： Mihir Tendulkar , David Chi
IPC分类号： H01L29/02 , H01L45/00 , H01L49/02 , H01L21/285
CPC分类号： H01L45/146 , H01L21/28506 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L28/24 , H01L45/06 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/1616 , H01L45/1641
摘要： Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.
摘要翻译： 本发明的实施例包括具有改进的器件性能和寿命的非易失性电阻随机存取存储器件的非易失性存储器件。 在一些实施例中，非易失性电阻随机存取存储器件包括二极管，金属氮化硅嵌入式电阻器和设置在第一电极层和第二电极层之间的电阻开关层。 在一些实施例中，形成电阻随机存取存储器件的方法包括形成二极管，形成金属氮化硅嵌入式电阻器，形成第一电极层，形成第二电极层，以及形成电阻开关层， 层和第二电极层。
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10.发明申请公开(公告)号：US20140363948A1
公开(公告)日：2014-12-11
申请号：US14468687
申请日：2014-08-26
发明人： Mihir Tendulkar , David Chi
IPC分类号： H01L45/00 , H01L21/285 , H01L49/02
CPC分类号： H01L45/146 , H01L21/28506 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L28/24 , H01L45/06 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/1616 , H01L45/1641
摘要： Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.
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