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公开(公告)号：US06263448B1
公开(公告)日：2001-07-17
申请号：US09169378
申请日：1998-10-09
IPC分类号： G06F104
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.
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公开(公告)号：US06226754B1
公开(公告)日：2001-05-01
申请号：US09169687
申请日：1998-10-09
申请人： Frederick A. Ware , Richard M. Barth , Donald C. Stark , Craig E. Hampel , Ely K. Tsern , Abhijit M. Abhyankar
发明人： Frederick A. Ware , Richard M. Barth , Donald C. Stark , Craig E. Hampel , Ely K. Tsern , Abhijit M. Abhyankar
IPC分类号： G06F104
CPC分类号： G11C7/1072 , G11C7/22
摘要： An electronic device with device timing constraints includes a set of connections coupled to an interconnect structure that carries row and column commands. A memory core stores data. A memory interface is connect to the set of connections and the memory core. The memory interface includes circuitry for generating memory core timing signals in accordance with the row commands and the column commands. The memory core timing signals have timing constraints to insure correct memory core operation. The memory interface circuitry includes individual delay components for adjusting the timing of selected timing signals of the memory core timing signals.
摘要翻译： 具有设备定时约束的电子设备包括耦合到承载行和列命令的互连结构的一组连接。 内存核心存储数据。 存储器接口连接到一组连接和存储器核心。 存储器接口包括用于根据行命令和列命令产生存储器核心定时信号的电路。 存储器核心定时信号具有时序约束，以确保正确的存储器核心操作。 存储器接口电路包括用于调整存储器核心定时信号的选定定时信号的定时的各个延迟部件。
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公开(公告)号：US08305839B2
公开(公告)日：2012-11-06
申请号：US13352177
申请日：2012-01-17
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
摘要翻译： 描述了具有存储器核心的存储器件。 存储器件包括时钟接收器电路，用于接收读取命令的第一接口，数据接口和用于接收功率模式信息的第二接口。 数据接口与第一个接口分开。 第二个接口与第一个接口和数据接口分开。 存储器件具有多个功率模式，包括时钟接收器电路，第一接口和数据接口关闭的第一模式; 时钟接收器被接通并且第一接口和数据接口被关闭的第二模式; 以及其中时钟接收器和第一接口被接通的第三模式。 在第三种模式下，当第一个接口接收到命令时，数据接口被打开，以响应命令输出数据。
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公开(公告)号：US20110090755A1
公开(公告)日：2011-04-21
申请号：US12975322
申请日：2010-12-21
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
摘要翻译： 描述了具有存储器核心的存储器件。 存储器件包括时钟接收器电路，用于接收读取命令的第一接口，数据接口和用于接收功率模式信息的第二接口。 数据接口与第一个接口分开。 第二个接口与第一个接口和数据接口分开。 存储器件具有多个功率模式，包括时钟接收器电路，第一接口和数据接口关闭的第一模式; 时钟接收器被接通并且第一接口和数据接口被关闭的第二模式; 以及其中时钟接收器和第一接口被接通的第三模式。 在第三种模式下，当第一个接口接收到命令时，数据接口被打开，以响应命令输出数据。
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公开(公告)号：US20100046314A1
公开(公告)日：2010-02-25
申请号：US12608209
申请日：2009-10-29
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.
摘要翻译： 描述了具有存储器核心的存储器件。 存储器件包括时钟接收器电路，控制接口，数据接口，延迟锁定环电路，读取流水线电路和用于提供内部时钟信号的电路。 时钟接收器电路接收外部时钟信号。 控制接口接收指定对存储器件的读取操作的命令。 数据接口在存储器件和外部信号线组之间传送数据。 延迟锁定环路电路，耦合到时钟接收器电路，以使用外部时钟信号产生内部时钟信号。 读取管线电路将从存储器核心访问的读取数据提供给数据接口。 响应于接收到指定读取操作的命令，该电路将内部时钟信号提供给读取管线电路。
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公开(公告)号：US07039782B2
公开(公告)日：2006-05-02
申请号：US10690402
申请日：2003-10-20
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1684 , Y02D10/14
摘要： A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.
摘要翻译： 公开了一种高速存储器系统，其中单个命令根据当前的操作模式对单个存储器件或多个存储器件进行控制。 这种控制可以影响一个或多个存储器件与存储器控制器之间的数据传输，以及存储器件的操作状态转换或功率模式转换。 类似地，相对低带宽的存储器件的各种配置作为有选择地控制的组进行响应以发送或接收高带宽数据。
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公开(公告)号：US06378018B1
公开(公告)日：2002-04-23
申请号：US09169506
申请日：1998-10-09
申请人： Ely K. Tsern , Thomas J. Holman , Richard M. Barth , Andrew V. Anderson , Paul G. Davis , Craig E. Hampel , Donald C. Stark , Abhijit M. Abhyankar
发明人： Ely K. Tsern , Thomas J. Holman , Richard M. Barth , Andrew V. Anderson , Paul G. Davis , Craig E. Hampel , Donald C. Stark , Abhijit M. Abhyankar
IPC分类号： G06F1300
CPC分类号： G06F13/4243 , G06F13/1694 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure. The memory controller may be configured to apply control information to the interconnect structure as an encoded device identification word. The memory devices may each include a decoder for interpreting the encoded device identification word. The memory controller may be configured to apply a memory device selection signal to the interconnect structure to selectively enable the memory devices.
摘要翻译： 存储器系统包括具有高速通道和低速通道的互连结构。 具有接口电路的存储器件耦合到互连结构。 接口电路包括用于耦合到高速通道的高功率接口和用于耦合到低速通道的低功率接口。 存储器件在低功率模式和高功率模式下工作。 存储器控制器耦合到互连结构的高速通道和低速通道。 存储器控制器被配置为通过低速信道发送控制信息以设置存储器件的功率模式。 存储器件在低功率模式下工作，在此期间高功率接收器电路被关闭。 存储器装置还可以在休眠模式下工作，在此模式期间内部时钟补偿电路被保留以保持相位信息。 存储器系统可以包括耦合到互连结构的菊花链引导件的多个存储器件。 存储器控制器可以被配置为将控制信息作为编码设备标识字应用于互连结构。 存储器件可以各自包括用于解释编码器件识别字的解码器。 存储器控制器可以被配置为将存储器件选择信号施加到互连结构以选择性地启用存储器件。
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公开(公告)号：US06718431B2
公开(公告)日：2004-04-06
申请号：US10053632
申请日：2002-01-18
申请人： Richard M. Barth , Ely K. Tsern , Mark A. Horowitz , Donald C. Stark , Craig E. Hampel , Frederick A. Ware , John B. Dillon
发明人： Richard M. Barth , Ely K. Tsern , Mark A. Horowitz , Donald C. Stark , Craig E. Hampel , Frederick A. Ware , John B. Dillon
IPC分类号： G06F1200
CPC分类号： G11C7/1006 , G06F13/1615 , G11C7/10 , G11C7/1039 , G11C8/12 , G11C11/4076
摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.
摘要翻译： 存储器设备具有构成流水线阶段的接口电路和存储器核心，每个阶段是与存储器核心相关联的通用序列中的步骤。 存储装置具有多个操作单元，例如预充电，感测，读取和写入，其处理操作单元耦合到的存储器核的原始操作。 存储装置还包括多个传输单元，其被配置为从外部连接获取信息，指定操作单元之一的操作并且在存储器核心和外部连接之间传送数据。 运输单元与运营单元同时运行作为流水线的附加阶段，从而创建一种在普通应用的存储器参考流下以高吞吐量和低服务时间运行的存储器件。
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公开(公告)号：US06701446B2
公开(公告)日：2004-03-02
申请号：US09887181
申请日：2001-06-21
IPC分类号： G06F104
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.
摘要翻译： 具有多个时钟域的存储器件。 将时钟分离到控制电路的不同部分，创建不同的时钟域。 根据需要依次打开不同的域以限制消耗的功率。 域的接通时间与存储器访问的等待时间重叠，使得功率控制对于访问存储器核心的用户是透明的。 存储器件可以根据所需的数据带宽在快速和慢时钟之间动态切换。 存储器接口上的数据带宽可以由存储器控制器进行监视，并且当其低于某个阈值时，可以使用较慢的时钟。 随着带宽需求的增加，时钟速度可以动态增加。
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公开(公告)号：US06226757B1
公开(公告)日：2001-05-01
申请号：US09169245
申请日：1998-10-09
申请人： Frederick A. Ware , Richard M. Barth , Donald C. Stark , Craig E. Hampel , Ely K. Tsern , Abhijit M. Abhyankar , Thomas J. Holman , Andrew V. Anderson , Peter D. MacWilliams
发明人： Frederick A. Ware , Richard M. Barth , Donald C. Stark , Craig E. Hampel , Ely K. Tsern , Abhijit M. Abhyankar , Thomas J. Holman , Andrew V. Anderson , Peter D. MacWilliams
IPC分类号： G06F104
CPC分类号： G06F13/4226
摘要： A digital system includes a clock line carrying a clock signal and a communication bus with a signal time of flight longer than a cycle of the clock signal. A master device is connected to the communication bus and the clock line. The master device selectively applies signals to the communication bus. A set of slave devices are connected to the communication bus and the clock line. Each slave device of the set of slave devices has an associated latency delay arising from its position on the communication bus. Each slave device includes delay circuitry to compensate for the associated latency delay such that the master device observes a uniform minimum latency for each slave device in response to applying signals to the communication bus.
摘要翻译： 一个数字系统包括一个带有时钟信号的时钟线和一个具有比时钟信号周期长的信号时间的通信总线。 主设备连接到通信总线和时钟线。 主设备选择性地向通信总线施加信号。 一组从设备连接到通信总线和时钟线。 一组从设备的每个从设备具有由其在通信总线上的位置产生的相关联的延迟延迟。 每个从设备包括延迟电路以补偿相关联的延迟延迟，使得主设备响应于向通信总线应用信号而观察到每个从设备的均匀最小等待时间。
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