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公开(公告)号：US20110287944A1
公开(公告)日：2011-11-24
申请号：US12783116
申请日：2010-05-19
申请人： Erica Folk , Patrick B. Shea , Andrew C. Loyd
发明人： Erica Folk , Patrick B. Shea , Andrew C. Loyd
CPC分类号： H01L39/2493 , H01L27/18
摘要： Methods of forming superconducting devices are disclosed. In one embodiment, the method can comprise depositing a protective barrier layer over a superconducting material layer, curing the protective barrier layer, depositing a photoresist material layer over the protective barrier layer and irradiating and developing the photoresist material layer to form an opening pattern in the photoresist material layer. The method can further comprise etching the protective barrier layer to form openings in the protective barrier layer based on the opening pattern, etching the superconductor material layer based on the openings in the protective barrier layer to form openings in the superconductor material layer that define a first set of superconductor material raised portins and stripping the photoresist material layer and the protective barrier layer.
摘要翻译： 公开了形成超导装置的方法。 在一个实施例中，该方法可以包括在超导材料层上沉积保护性阻挡层，固化保护性阻挡层，在保护性阻挡层上沉积光致抗蚀剂材料层并照射和显影光致抗蚀剂材料层以在 光致抗蚀剂材料层。 该方法还可以包括蚀刻保护性阻挡层，以基于开口图案在保护阻挡层中形成开口，基于保护性阻挡层中的开口蚀刻超导体材料层，以在超导体材料层中形成限定第一 一组超导体材料凸起的孔并剥离光致抗蚀剂材料层和保护性阻挡层。
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公开(公告)号：US08735326B2
公开(公告)日：2014-05-27
申请号：US12783116
申请日：2010-05-19
申请人： Erica Folk , Patrick B. Shea , Andrew C. Loyd
发明人： Erica Folk , Patrick B. Shea , Andrew C. Loyd
IPC分类号： H01L39/24
CPC分类号： H01L39/2493 , H01L27/18
摘要： Methods of forming superconducting devices are disclosed. In one embodiment, the method can comprise depositing a protective barrier layer over a superconducting material layer, curing the protective barrier layer, depositing a photoresist material layer over the protective barrier layer and irradiating and developing the photoresist material layer to form an opening pattern in the photoresist material layer. The method can further comprise etching the protective barrier layer to form openings in the protective barrier layer based on the opening pattern, etching the superconductor material layer based on the openings in the protective barrier layer to form openings in the superconductor material layer that define a first set of superconductor material raised portins and stripping the photoresist material layer and the protective barrier layer.
摘要翻译： 公开了形成超导装置的方法。 在一个实施例中，该方法可以包括在超导材料层上沉积保护性阻挡层，固化保护性阻挡层，在保护性阻挡层上沉积光致抗蚀剂材料层并照射和显影光致抗蚀剂材料层以在 光致抗蚀剂材料层。 该方法还可以包括蚀刻保护性阻挡层，以基于开口图案在保护阻挡层中形成开口，基于保护性阻挡层中的开口蚀刻超导体材料层，以在超导体材料层中形成限定第一 一组超导体材料凸起的孔并剥离光致抗蚀剂材料层和保护性阻挡层。
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公开(公告)号：US09748506B1
公开(公告)日：2017-08-29
申请号：US15340499
申请日：2016-11-01
申请人： James T. Kelliher , Monica P. Lilly , Robert S. Howell , Wayne Stephen Miller , Patrick B. Shea , Matthew J. Walker , William J. Sweet
发明人： James T. Kelliher , Monica P. Lilly , Robert S. Howell , Wayne Stephen Miller , Patrick B. Shea , Matthew J. Walker , William J. Sweet
CPC分类号： H01L51/0533 , H01L51/0048 , H01L51/0566
摘要： One example includes a semiconductor device. The semiconductor device include a carbon nanotube substrate, a self-assembled monolayer, and a gate oxide. The self-assembled monolayer overlies the carbon nanotube substrate and is comprised of molecules each including a tail group, a carbon backbone, and a head group. The gate oxide overlies the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.
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4.发明授权Method of making bipolar junction transistor by forming base epitaxy region on etched opening in DARC layer 有权通过在DARC层的蚀刻开口上形成基底外延区域制作双极结晶体管的方法公开(公告)号：US09142546B2
公开(公告)日：2015-09-22
申请号：US14098199
申请日：2013-12-05
IPC分类号： H01L21/336 , H01L21/331 , H01L21/338 , H01L21/337 , H01L21/8249 , H01L21/8222 , H01L27/06 , H01L27/092 , H01L29/737 , H01L29/66 , H01L29/165 , H01L21/02 , H01L21/306 , H01L21/265
CPC分类号： H01L27/0711 , H01L21/02532 , H01L21/02595 , H01L21/31144 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L27/092 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/66242 , H01L29/737 , H01L29/7371 , H01L29/7378
摘要： A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.
摘要翻译： 提供了形成双极晶体管器件的方法。 该方法包括在集电极有源区域上的衬底上沉积集电极电介质层，在集电极电介质层上沉积电介质抗反射（DARC）层，干蚀刻掉DARC层中的基底开口，并湿法蚀刻掉部分 的基底开口中的集电极介电层，以提供到基板的延伸的基部开口。 该方法还包括进行基底沉积以在延伸的基底开口中形成基底外延区域，并且延伸在DARC层的第一和第二部分上，该DARC层由于干蚀刻而残留在DARC层中的基底开口处，并形成 在基底外延区域上的发射极区域。
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公开(公告)号：US20130119351A1
公开(公告)日：2013-05-16
申请号：US13294473
申请日：2011-11-11
IPC分类号： H01L39/22
CPC分类号： G06N99/002 , H01L39/223 , H01L39/2493
摘要： Methods are provided of forming a Josephson junction (JJ) quantum bit (qubit). In one embodiment, the method comprises forming a JJ trilayer on a substrate. The JJ trilayer is comprised of a dielectric layer sandwiched between a bottom superconductor material layer and a top superconductor material layer. The method further comprises performing a thermal hardening process on the JJ trilayer to control diffusion of the dielectric layer into the bottom superconductor material layer and the top superconductor material layer, and etching openings in the JJ trilayer to form one or more JJ qubits.
摘要翻译： 提供了形成约瑟夫逊结（JJ）量子位（量子位）的方法。 在一个实施方案中，该方法包括在基底上形成JJ三层。 JJ三层由夹在底部超导体材料层和顶部超导体材料层之间的介电层构成。 该方法还包括对JJ三层进行热硬化处理以控制电介质层扩散到底部超导体材料层和顶部超导体材料层中，以及蚀刻JJ三层中的开口以形成一个或多个JJ量子位。
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公开(公告)号：US09355362B2
公开(公告)日：2016-05-31
申请号：US13294473
申请日：2011-11-11
CPC分类号： G06N99/002 , H01L39/223 , H01L39/2493
摘要： Methods are provided of forming a Josephson junction (JJ) quantum bit (qubit). In one embodiment, the method comprises forming a JJ trilayer on a substrate. The JJ trilayer is comprised of a dielectric layer sandwiched between a bottom superconductor material layer and a top superconductor material layer. The method further comprises performing a thermal hardening process on the JJ trilayer to control diffusion of the dielectric layer into the bottom superconductor material layer and the top superconductor material layer, and etching openings in the JJ trilayer to form one or more JJ qubits.
摘要翻译： 提供了形成约瑟夫逊结（JJ）量子位（量子位）的方法。 在一个实施方案中，该方法包括在基底上形成JJ三层。 JJ三层由夹在底部超导体材料层和顶部超导体材料层之间的介电层构成。 该方法还包括对JJ三层进行热硬化处理以控制电介质层扩散到底部超导体材料层和顶部超导体材料层中，以及蚀刻JJ三层中的开口以形成一个或多个JJ量子位。
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公开(公告)号：US10069093B2
公开(公告)日：2018-09-04
申请号：US15642066
申请日：2017-07-05
申请人： James T. Kelliher , Monica P. Lilly , Robert S. Howell , Wayne Stephen Miller , Patrick B. Shea , Matthew J. Walker , William J. Sweet
发明人： James T. Kelliher , Monica P. Lilly , Robert S. Howell , Wayne Stephen Miller , Patrick B. Shea , Matthew J. Walker , William J. Sweet
摘要： One example includes a semiconductor device. The semiconductor device include a carbon nanotube substrate, a self-assembled monolayer, and a gate oxide. The self-assembled monolayer overlies the carbon nanotube substrate and is comprised of molecules each including a tail group, a carbon backbone, and a head group. The gate oxide overlies the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.
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8.发明授权公开(公告)号：US09812445B2
公开(公告)日：2017-11-07
申请号：US14829487
申请日：2015-08-18
IPC分类号： H01L27/07 , H01L29/10 , H01L29/08 , H01L29/737 , H01L29/66 , H01L27/06 , H01L21/8249
CPC分类号： H01L27/0711 , H01L21/02532 , H01L21/02595 , H01L21/31144 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L27/092 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/66242 , H01L29/737 , H01L29/7371 , H01L29/7378
摘要： A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.
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公开(公告)号：US09646259B2
公开(公告)日：2017-05-09
申请号：US14460988
申请日：2014-08-15
CPC分类号： G06N99/002 , H01L39/223 , H01L39/2493
摘要： A Josephson junction (JJ) quantum bit (qubits) arranged on a substrate is provided. In one embodiment, each qubit comprises a dielectric layer, a superconductor base layer portion underlying the dielectric layer and a first dielectric diffused region adjacent a dielectric layer/superconductor base layer portion junction. The qubit further comprise a superconductor mesa layer portion overlying the dielectric layer and having a second dielectric diffused region adjacent a dielectric layer/superconductor mesa layer portion junction, the first and second dielectric diffused regions mitigating further diffusion from other semiconductor processes on the plurality of qubits.
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