公开(公告)号：US09748506B1

公开(公告)日：2017-08-29

申请号：US15340499

申请日：2016-11-01

申请人： James T. Kelliher ,  Monica P. Lilly ,  Robert S. Howell ,  Wayne Stephen Miller ,  Patrick B. Shea ,  Matthew J. Walker ,  William J. Sweet

发明人： James T. Kelliher ,  Monica P. Lilly ,  Robert S. Howell ,  Wayne Stephen Miller ,  Patrick B. Shea ,  Matthew J. Walker ,  William J. Sweet

IPC分类号： H01L29/76 ,  H01L51/05 ,  H01L51/00

CPC分类号： H01L51/0533 ,  H01L51/0048 ,  H01L51/0566

摘要： One example includes a semiconductor device. The semiconductor device include a carbon nanotube substrate, a self-assembled monolayer, and a gate oxide. The self-assembled monolayer overlies the carbon nanotube substrate and is comprised of molecules each including a tail group, a carbon backbone, and a head group. The gate oxide overlies the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.

公开(公告)号：US10069093B2

公开(公告)日：2018-09-04

申请号：US15642066

申请日：2017-07-05

申请人： James T. Kelliher ,  Monica P. Lilly ,  Robert S. Howell ,  Wayne Stephen Miller ,  Patrick B. Shea ,  Matthew J. Walker ,  William J. Sweet

发明人： James T. Kelliher ,  Monica P. Lilly ,  Robert S. Howell ,  Wayne Stephen Miller ,  Patrick B. Shea ,  Matthew J. Walker ,  William J. Sweet

IPC分类号： H01L51/00 ,  H01L29/76 ,  H01L51/05

摘要： One example includes a semiconductor device. The semiconductor device include a carbon nanotube substrate, a self-assembled monolayer, and a gate oxide. The self-assembled monolayer overlies the carbon nanotube substrate and is comprised of molecules each including a tail group, a carbon backbone, and a head group. The gate oxide overlies the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.

公开(公告)号：US10854600B2

公开(公告)日：2020-12-01

申请号：US16577629

申请日：2019-09-20

申请人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L21/338 ,  H01L27/088 ,  H01L21/8252 ,  H01L21/308 ,  H01L29/66 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06

摘要： A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.

公开(公告)号：US10186742B2

公开(公告)日：2019-01-22

申请号：US13803385

申请日：2013-03-14

申请人： Marc Eisenzweig Sherwin ,  Robert S. Howell ,  Pavel Borodulin ,  Harold Clifton Hearne, III ,  Nabil Abdel-Meguid El-Hinnawy ,  Robert Miles Young

发明人： Marc Eisenzweig Sherwin ,  Robert S. Howell ,  Pavel Borodulin ,  Harold Clifton Hearne, III ,  Nabil Abdel-Meguid El-Hinnawy ,  Robert Miles Young

IPC分类号： H01P1/10 ,  H01L45/02 ,  H03K19/173 ,  H01L45/00 ,  H03K19/177

摘要： One embodiment of the invention includes a reconfigurable circuit comprising a phase-change material switch. The phase-change material switch includes an actuation portion configured to receive a control signal having one of a first state and a second state and to emit a first heat profile in response to the first state of the control signal and a second heat profile in response to the second state of the control signal. The phase-change material switch also includes a switch portion comprising a phase-change material in proximity with the actuation portion. The switch portion can be selectable between a conducting state in response to the first heat profile to conduct an input signal from an input to an output of the phase-change material switch and a blocking state in response to the second heat profile to substantially block the input signal from the input to the output.

公开(公告)号：US07514301B2

公开(公告)日：2009-04-07

申请号：US11524246

申请日：2006-09-21

申请人： Garrett A. Storaska ,  Robert S. Howell

发明人： Garrett A. Storaska ,  Robert S. Howell

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1203 ,  B81C1/0019 ,  B82Y10/00 ,  B82Y30/00 ,  H01F41/041 ,  H01L21/84 ,  H01L27/10

摘要： A method for fabricating nanocoils and improved nanocoils fabricated therefrom. Embodiments of the method utilizing deep reactive ion etching (DRIE). A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer, in which SOI wafer includes buried oxide layer, patterning one or more devices into a layer of silicon on top of the buried oxide layer, depositing tensile stressed nitride layer on the top silicon layer, patterning coiling arm structure on top silicon layer, patterning an overlapping etch window mask on bottom side of SOI wafer using, in which patterning overlapping etch window mask removes SOI wafer and exposes buried oxide layer in width greater than coiling arm structure, and releasing coiling arm structure so that coiling arm coils to form nanocoil. In embodiments, DRIE is utilized to pattern the overlapping etch window mask.

摘要翻译： 一种用于制造纳米线和由其制造的改进的纳米薄膜的方法。 利用深反应离子蚀刻（DRIE）的方法的实施例。 制造纳米线的方法包括提供绝缘体上硅（SOI）晶片，其中SOI晶片包括掩埋氧化物层，将一个或多个器件图案化成掩埋氧化物层顶部的硅层，沉积拉应力氮化物层 在顶层硅层上，在顶部硅层上图案化卷取臂结构，在SOI晶片的底侧上构图重叠的蚀刻窗口掩模，其中图案化重叠的蚀刻窗口掩模移除SOI晶片并暴露出大于卷取臂的宽度的掩埋氧化物层 结构和释放卷取臂结构，使卷绕臂线圈形成纳米油。 在实施例中，DRIE用于对重叠的蚀刻窗口掩模进行图案化。

公开(公告)号：US10804387B1

公开(公告)日：2020-10-13

申请号：US16360828

申请日：2019-03-21

申请人： Josephine Bea Chang ,  Robert S. Howell ,  Matthew R. King

发明人： Josephine Bea Chang ,  Robert S. Howell ,  Matthew R. King

IPC分类号： H01L29/778 ,  H01L29/15 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02

摘要： A vertical transistor is provided that includes a base structure and a superlattice structure overlying the base structure. The superlattice structure comprises a multichannel ridge having sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. The vertical transistor also includes a source region that overlies the base structure and is in contact with a first end of the superlattice structure, a floating drain that overlies the base structure and is in contact with a second end of the superlattice structure, and a drain. When the vertical transistor is in an ‘ON’ state, current flows from the source region through the channels of the multichannel ridge to the floating drain, which funnels the current to the drain through at least a portion of the base structure.

公开(公告)号：US10468406B2

公开(公告)日：2019-11-05

申请号：US14509750

申请日：2014-10-08

申请人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/15 ,  H01L27/088 ,  H01L21/8252 ,  H01L21/308 ,  H01L29/66 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06

摘要： A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.

公开(公告)号：US09773897B2

公开(公告)日：2017-09-26

申请号：US14676285

申请日：2015-04-01

申请人： Bettina A. Nechay ,  Robert S. Howell ,  Eric J. Stewart ,  Howell George Henry ,  Justin Andrew Parke ,  Ronald G. Freitag

发明人： Bettina A. Nechay ,  Robert S. Howell ,  Eric J. Stewart ,  Howell George Henry ,  Justin Andrew Parke ,  Ronald G. Freitag

IPC分类号： H01L29/02 ,  H01L29/10 ,  H01L29/778 ,  H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/20

CPC分类号： H01L29/7783 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/7851

摘要： A transistor device is provided that includes a base structure and a superlattice structure that overlies the base structure. The superlattice structure comprises a multichannel ridge having sides that extend to the base structure. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. A three-sided gate configuration is provided that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth. The three-sided gate configuration is configured to re-distribute peak electric fields along the three-sided gate configuration to facilitate the increase in breakdown voltage of the transistor device.

公开(公告)号：US09755021B2

公开(公告)日：2017-09-05

申请号：US15186193

申请日：2016-06-17

申请人： Karen M. Renaldo ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Harlan Carl Cramer ,  Justin Andrew Parke ,  Matthew Russell King

发明人： Karen M. Renaldo ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Harlan Carl Cramer ,  Justin Andrew Parke ,  Matthew Russell King

IPC分类号： H01L29/66 ,  H01L29/15 ,  H01L29/778 ,  H01L21/02 ,  H01L21/76 ,  H01L29/06 ,  H01L21/302 ,  H01L29/423 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L21/3065 ,  H01L21/768 ,  H01L29/205 ,  H01L29/417 ,  H01L29/51

CPC分类号： H01L29/155 ,  H01L21/0254 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/76877 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterorstructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.

公开(公告)号：US09466679B2

公开(公告)日：2016-10-11

申请号：US14459006

申请日：2014-08-13

申请人： Eric J. Stewart ,  Howell George Henry ,  Robert S. Howell ,  Matthew Russell King ,  Justin Andrew Parke ,  Bettina Nechay ,  Harlan Carl Cramer ,  Karen Marie Renaldo ,  Ronald G. Freitag

发明人： Eric J. Stewart ,  Howell George Henry ,  Robert S. Howell ,  Matthew Russell King ,  Justin Andrew Parke ,  Bettina Nechay ,  Harlan Carl Cramer ,  Karen Marie Renaldo ,  Ronald G. Freitag

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC分类号： H01L29/42316 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7783

摘要： A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end.