公开(公告)号：US09748506B1

公开(公告)日：2017-08-29

申请号：US15340499

申请日：2016-11-01

申请人： James T. Kelliher ,  Monica P. Lilly ,  Robert S. Howell ,  Wayne Stephen Miller ,  Patrick B. Shea ,  Matthew J. Walker ,  William J. Sweet

发明人： James T. Kelliher ,  Monica P. Lilly ,  Robert S. Howell ,  Wayne Stephen Miller ,  Patrick B. Shea ,  Matthew J. Walker ,  William J. Sweet

IPC分类号： H01L29/76 ,  H01L51/05 ,  H01L51/00

CPC分类号： H01L51/0533 ,  H01L51/0048 ,  H01L51/0566

摘要： One example includes a semiconductor device. The semiconductor device include a carbon nanotube substrate, a self-assembled monolayer, and a gate oxide. The self-assembled monolayer overlies the carbon nanotube substrate and is comprised of molecules each including a tail group, a carbon backbone, and a head group. The gate oxide overlies the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.

公开(公告)号：US10069093B2

公开(公告)日：2018-09-04

申请号：US15642066

申请日：2017-07-05

申请人： James T. Kelliher ,  Monica P. Lilly ,  Robert S. Howell ,  Wayne Stephen Miller ,  Patrick B. Shea ,  Matthew J. Walker ,  William J. Sweet

发明人： James T. Kelliher ,  Monica P. Lilly ,  Robert S. Howell ,  Wayne Stephen Miller ,  Patrick B. Shea ,  Matthew J. Walker ,  William J. Sweet

IPC分类号： H01L51/00 ,  H01L29/76 ,  H01L51/05

摘要： One example includes a semiconductor device. The semiconductor device include a carbon nanotube substrate, a self-assembled monolayer, and a gate oxide. The self-assembled monolayer overlies the carbon nanotube substrate and is comprised of molecules each including a tail group, a carbon backbone, and a head group. The gate oxide overlies the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.

公开(公告)号：US11342440B2

公开(公告)日：2022-05-24

申请号：US16518381

申请日：2019-07-22

申请人： Ishan Wathuthanthri ,  Ken Alfred Nagamatsu ,  William J. Sweet ,  James T. Kelliher ,  John S. Mason, Jr. ,  Jonah Paul Sengupta

发明人： Ishan Wathuthanthri ,  Ken Alfred Nagamatsu ,  William J. Sweet ,  James T. Kelliher ,  John S. Mason, Jr. ,  Jonah Paul Sengupta

IPC分类号： H01L29/778 ,  H01L29/15 ,  H01L29/66 ,  H01L21/56 ,  H01L23/31 ,  H01L29/06 ,  H01L21/02

摘要： A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.

公开(公告)号：US09653398B1

公开(公告)日：2017-05-16

申请号：US14962981

申请日：2015-12-08

申请人： James T. Kelliher ,  Sandro J. Di Giacomo ,  Cory E. Sherman ,  Brian P. Wagner

发明人： James T. Kelliher ,  Sandro J. Di Giacomo ,  Cory E. Sherman ,  Brian P. Wagner

IPC分类号： H01L39/24 ,  H01L23/532 ,  H01L39/02

CPC分类号： H01L23/53285 ,  H01L21/76891 ,  H01L39/2406

摘要： A method of forming a superconductor device is provided. The method includes depositing a non-oxide based dielectric layer over a substrate, depositing a photoresist material layer over the non-oxide based dielectric layer, irradiating and developing the photoresist material layer to form a via pattern in the photoresist material layer, and etching the non-oxide based dielectric layer to form openings in the non-oxide based dielectric layer based on the via pattern. The method further comprises stripping the photoresist material layer, and filling the openings in the non-oxide based dielectric with a superconducting material to form a set of superconducting contacts.

公开(公告)号：US07202187B2

公开(公告)日：2007-04-10

申请号：US10710257

申请日：2004-06-29

申请人： Ravikumar Ramachandran ,  James T. Kelliher ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Ravikumar Ramachandran ,  James T. Kelliher ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L21/469 ,  H01L21/31

CPC分类号： H01L21/3185 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/823864

摘要： A silicon nitride spacer material for use in forming a PFET device and a method for making the spacer includes the use of a dual-frequency plasma enhanced CVD process wherein the temperature is in the range depositing a silicon nitride layer by means of a low-temperature dual-frequency plasma enhanced CVD process, at a temperature in the range 400° C. to 550° C. The process pressure is in the range 2 Torr to 5 Torr. The low frequency power is in the range 0 W to 50 W, and the high frequency power is in the range 90 W to 110 W. The precursor gases of silane, ammonia and nitrogen flow at flow rates in the ratio 240:3200:4000 sccm. The use of the silicon nitride spacer of the invention to form a PFET device having a dual spacer results in a 10%–15% performance improvement compared to a similar PFET device having a silicon nitride spacer formed by a RTCVD process.

摘要翻译： 用于形成PFET器件的氮化硅间隔物材料和用于制造间隔物的方法包括使用双频等离子体增强CVD工艺，其中温度在通过低温下沉积氮化硅层的范围 双频等离子体增强CVD工艺，温度范围为400°C至550°C。工艺压力范围为2 Torr至5 Torr。 低频功率在0W至50W的范围内，高频功率在90W至110W的范围内。硅烷，氨和氮气的前体气体以240：3200：4000的比例流动 sccm。 与具有通过RTCVD工艺形成的氮化硅间隔物的类似PFET器件相比，使用本发明的氮化硅间隔物形成具有双间隔物的PFET器件导致10％-15％的性能提高。

公开(公告)号：US10985059B2

公开(公告)日：2021-04-20

申请号：US16178306

申请日：2018-11-01

申请人： Brian Paul Wagner ,  Christopher F. Kirby ,  Michael Rennie ,  James T. Kelliher ,  Khyhouth Lim

发明人： Brian Paul Wagner ,  Christopher F. Kirby ,  Michael Rennie ,  James T. Kelliher ,  Khyhouth Lim

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L39/24

摘要： A method is provided of forming a superconductor device interconnect structure. The method comprises forming a first dielectric layer overlying a substrate and forming a superconducting interconnect element in the first dielectric layer. The superconducting interconnect element includes a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The superconductor device interconnect structure is moved into a dielectric deposition chamber. The method further comprises performing a cleaning process on a top surface of the first interconnect layer in the dielectric deposition chamber to remove oxidization from a top surface of the first interconnect layer, and depositing a second dielectric layer over the first interconnect layer in the dielectric deposition chamber.

公开(公告)号：US20090176367A1

公开(公告)日：2009-07-09

申请号：US11970748

申请日：2008-01-08

申请人： Heidi Baks ,  James T. Kelliher ,  Huang Liu

发明人： Heidi Baks ,  James T. Kelliher ,  Huang Liu

IPC分类号： H01L21/768

CPC分类号： H01L21/02304 ,  H01L21/312 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A back-end-of-line (BEOL) interconnect structure and a method of forming an interconnect structure. The interconnect structure comprises a conductor, such as copper, embedded in a dielectric layer, and a low-k dielectric capping layer, which acts as a diffusion barrier, on the conductor. A method of forming the BEOL interconnect structure is disclosed, where the capping layer is deposited using plasma-enhanced chemical vapor deposition (PECVD) and is comprised of Si, C, H, and N. The interconnect structure provides improved oxygen diffusion resistance and improved barrier qualities allowing for a reduction in film thickness.

摘要翻译： 后端行（BEOL）互连结构和形成互连结构的方法。 互连结构包括在导体上作为扩散阻挡层的埋入电介质层的导体（例如铜）和用作扩散阻挡层的低k电介质封盖层。 公开了形成BEOL互连结构的方法，其中使用等离子体增强化学气相沉积（PECVD）沉积覆盖层并且由Si，C，H和N组成。互连结构提供改善的耐氧扩散性和改进的 屏障质量允许减少膜厚度。