公开(公告)号：US5862316A

公开(公告)日：1999-01-19

申请号：US674276

申请日：1996-07-01

申请人： Erik E. Hagersten ,  John R. Catenzaro ,  William A. Nesheim ,  Monica C. Wong-Chan ,  Robert C. Zak, Jr. ,  Paul N. Loewenstein

发明人： Erik E. Hagersten ,  John R. Catenzaro ,  William A. Nesheim ,  Monica C. Wong-Chan ,  Robert C. Zak, Jr. ,  Paul N. Loewenstein

IPC分类号： G06F11/34 ,  G06F11/00 ,  G06F11/22 ,  G06F12/08

CPC分类号： G06F11/2205 ,  Y10S707/99952

摘要： Protocol agents involved in the performance of global coherency activity detect errors with respect to the activity being performed. The errors are logged by a computer system such that diagnostic software may be executed to determine the error detected and to trace the error to the erring software or hardware. In particular, information regarding the first error to be detected is logged. Subsequent errors may receive more or less logging depending upon programmable configuration values. Additionally, those errors which receive full logging may be programmably selected via error masks. The protocol agents each comprise multiple independent state machines which independently process requests. If the request which a particular state machine is processing results in an error, the particular state machine may enter a freeze state. Information regarding the request which is collected by the state machine may thereby be saved for later access. A state machine freezes upon detection of the error if a maximum number of the multiple state machines are not already frozen and the aforementioned error mask indicates that full error logging is employed for the detected error. Therefore, at least a minimum number of the multiple state machines remain functioning even in the presence of a large number of errors. Still further, prior to entering the freeze state, the protocol state machines may transition through a recovery state in which resources not used for error logging purposes are freed from the erring request.

摘要翻译： 参与执行全局一致性活动的协议代理检测相对于正在执行的活动的错误。 这些错误由计算机系统记录，使得可以执行诊断软件以确定检测到的错误并将错误跟踪到错误的软件或硬件。 特别地，记录关于要检测的第一错误的信息。 随后的错误可能会根据可编程的配置值接收或多或少的记录。 此外，可以通过错误掩码可编程地选择接收完整日志记录的错误。 协议代理各自包括独立处理请求的多个独立状态机。 如果特定状态机正在处理的请求导致错误，则特定状态机可能进入冻结状态。 关于由国家机器收集的关于请求的信息可以被保存以供稍后访问。 如果多个状态机的最大数量尚未冻结，并且上述错误掩码表示对于检测到的错误采用全错误记录，则状态机将在检测到错误后冻结。 因此，即使存在大量错误，至少多个状态机的最小数量也保持运行。 此外，在进入冻结状态之前，协议状态机可以转换到恢复状态，其中不用于错误记录的资源的资源从错误请求中解除。

公开(公告)号：US5881303A

公开(公告)日：1999-03-09

申请号：US674327

申请日：1996-07-01

申请人： Erik E. Hagersten ,  Paul N. Loewenstein ,  Monica C. Wong-Chan

发明人： Erik E. Hagersten ,  Paul N. Loewenstein ,  Monica C. Wong-Chan

IPC分类号： G06F15/16 ,  G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0813 ,  G06F12/0828 ,  G06F2212/507

摘要： A computer system includes multiple processing nodes, each of which is divided into subnodes. Transactions from a particular subnode are performed in the order presented by that subnode. Therefore, when a first transaction from the subnode is delayed to allow performance of coherency activity with other processing nodes, subsequent transactions from that subnode are delayed as well. Additionally, coherency activity for the subsequent transactions may be initiated in accordance with a prefetch method assigned to the subsequent transactions. In this manner, the delay associated with the ordering constraints of the system may be concurrently experienced with the delay associated with any coherency activity which may need to be performed in response to the subsequent transactions. In order to respect the ordering constraints imposed by the computer system, a system interface within the processing nodes employs an early completion policy for prefetch operations. If prefetch coherency activity for a transaction completes prior to coherency activity for another transaction from the same subnode, the early completion policy assigned to that transaction is enacted. In a drop policy, the data corresponding to the transaction is discarded. A write policy is also defined in which data received in response to the prefetch coherency activity is stored in the local memory. Lastly, a clear policy may be enforced in which the coherency activity is indicated to be complete.

摘要翻译： 计算机系统包括多个处理节点，每个节点分为子节点。 来自特定子节点的事务以该子节点呈现的顺序执行。 因此，当来自子节点的第一事务被延迟以允许与其他处理节点执行一致性活动时，来自该子节点的后续事务也被延迟。 此外，可以根据分配给后续交易的预取方法来发起后续交易的一致性活动。 以这种方式，与系统的排序约束相关联的延迟可以与可能需要响应于后续事务执行的任何一致性活动相关联的延迟同时经历。 为了尊重计算机系统施加的排序约束，处理节点内的系统接口采用预取操作的早期完成策略。 如果事务的预取一致性活动在来自相同子节点的另一个事务的一致性活动之前完成，则分配给该事务的早期完成策略被颁布。 在丢弃策略中，与事务相对应的数据被丢弃。 还定义了写策略，其中响应于预取一致性活动接收的数据被存储在本地存储器中。 最后，可以执行明确的策略，其中一致性活动被指示为完整的。

公开(公告)号：US5958019A

公开(公告)日：1999-09-28

申请号：US674328

申请日：1996-07-01

申请人： Erik E. Hagersten ,  Robert C. Zak, Jr. ,  Shaw-Wen Yang ,  Aleksandr Guzovskiy ,  William A. Nesheim ,  Monica C. Wong-Chan ,  Hien Nguyen

发明人： Erik E. Hagersten ,  Robert C. Zak, Jr. ,  Shaw-Wen Yang ,  Aleksandr Guzovskiy ,  William A. Nesheim ,  Monica C. Wong-Chan ,  Hien Nguyen

IPC分类号： G06F9/52 ,  G06F9/46 ,  G06F12/08 ,  G06F13/42

CPC分类号： G06F9/52 ,  G06F12/0828

摘要： When a processor within a computer system performs a synchronization operation, the system interface within the node delays subsequent transactions from the processor until outstanding coherency activity is completed. Therefore, the computer system may employ asynchronous operations. The synchronization operations may be used when needed to guarantee global completion of one or more prior asynchronous operations. In one embodiment, the synchronization operation is placed into a queue within the system interface. When the synchronization operation reaches the head of the queue, it may be initiated within the system interface. The system interface further includes a request agent comprising multiple control units, each of which may concurrently service coherency activity with respect to a different transaction. Furthermore, the system interface includes a synchronization control vector register which stores a bit for each control unit. Upon initiation of the synchronization operation within the system interface, bits corresponding to those control units which are performing coherency activity (i.e. those which are not idle) are set while other bits are cleared. As each control unit returns to the idle state, the corresponding bit is cleared as well. Once all the bits within the synchronization control vector register are cleared, the coherency activity which was outstanding when the synchronization operation was initiated is complete. The synchronization operation may then be completed.

摘要翻译： 当计算机系统内的处理器执行同步操作时，节点内的系统接口会延迟来自处理器的后续事务，直到完成一致的一致性活动。 因此，计算机系统可以采用异步操作。 当需要保证一个或多个在先的异步操作的全局完成时，可以使用同步操作。 在一个实施例中，同步操作被放置在系统接口内的队列中。 当同步操作到达队列的头部时，可以在系统界面内启动。 该系统接口还包括一个包含多个控制单元的请求代理，每个控制单元可以相对于不同的事务同时提供一致性活动。 此外，系统接口包括存储每个控制单元的位的同步控制向量寄存器。 在系统接口中启动同步操作之后，在执行一致性活动的那些控制单元（即那些不空闲的）的对应的位被设置，而其它位被清除。 当每个控制单元返回到空闲状态时，相应的位也被清除。 一旦清除了同步控制向量寄存器中的所有位，完成了同步操作启动时未完成的一致性活动。 然后可以完成同步操作。

公开(公告)号：US06360337B1

公开(公告)日：2002-03-19

申请号：US09238246

申请日：1999-01-27

申请人： Robert C. Zak ,  Hien H. Nguyen ,  Monica C. Wong-Chan

发明人： Robert C. Zak ,  Hien H. Nguyen ,  Monica C. Wong-Chan

IPC分类号： G06F1100

CPC分类号： G06F11/3409 ,  G06F11/3466 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2201/885

摘要： A performance counter to monitor a plurality of events that may occur in a component within a computer system during a monitoring period or testing period. The monitoring results, which are provided upon completion of the performance testing, may be used to provide histogram representations of the component performance. In one embodiment, the performance counter comprises a first storage, a second storage, programmable control logic, and a counting mechanism. The first storage is configured to store information indicative of a plurality of events to be monitored and the monitoring period for each event. The second storage is configured to store counting results obtained during the testing period. A counting mechanism, which is coupled to the second storage, is configured to monitor the occurrence of the events in the component under test. The counting mechanism is coupled to the control logic and the control logic is coupled to the first storage.

摘要翻译： 一种性能计数器，用于在监视期间或测试期间监视可能在计算机系统内的组件中发生的多个事件。 在性能测试完成后提供的监视结果可用于提供组件性能的直方图表示。 在一个实施例中，性能计数器包括第一存储器，第二存储器，可编程控制逻辑器件和计数机构。 第一存储器被配置为存储指示要监视的多个事件的信息和每个事件的监视周期。 第二存储器被配置为存储在测试期间获得的计数结果。 耦合到第二存储器的计数机构被配置为监视被测组件中的事件的发生。 计数机制耦合到控制逻辑，并且控制逻辑耦合到第一存储器。

公开(公告)号：US5590283A

公开(公告)日：1996-12-31

申请号：US380854

申请日：1995-01-27

申请人： W. Daniel Hillis ,  David C. Douglas ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  Monica C. Wong-Chan

发明人： W. Daniel Hillis ,  David C. Douglas ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  Monica C. Wong-Chan

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F15/173 ,  G06F15/80 ,  G06F15/163

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555 ,  G06F2201/88

摘要： A digital computer comprises a plurality of processing elements, a communications router, and a control network. Each processing element performs data processing operations in connection with commands, at least some of the processing elements performing the data processing operations in connection with the commands in messages they receive over the control network. Each processing element also generates and receives data transfer messages, each including an address portion containing an address, for transfer to another processing element as identified by the address. At least one of the processing elements further generates the control network messages for transfer over the communications router. The communications router comprises router nodes interconnected in the form of a "fat-tree," and the control network comprises control network nodes interconnected in the form of a tree, with the processing elements being connected at the leaf nodes of the respective communications router and control network.

摘要翻译： 数字计算机包括多个处理元件，通信路由器和控制网络。 每个处理单元执行与命令有关的数据处理操作，至少一些处理单元通过控制网络接收的消息中的命令进行数据处理操作。 每个处理元件还产生和接收数据传送消息，每个数据传送消息包括包含地址的地址部分，用于传送到由该地址识别的另一个处理元件。 处理元件中的至少一个进一步生成用于通过通信路由器传送的控制网络消息。 通信路由器包括以“胖树”形式互连的路由器节点，并且控制网络包括以树形式互连的控制网络节点，处理元件连接在相应通信路由器的叶节点处， 控制网络。

公开(公告)号：US06449667B1

公开(公告)日：2002-09-10

申请号：US09354425

申请日：1999-07-16

申请人： Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  Monica C. Wong-Chan ,  David C. Douglas

发明人： Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  Monica C. Wong-Chan ,  David C. Douglas

IPC分类号： G06F1300

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  G06F2201/88 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555

摘要： A digital computer comprising a plurality of processors interconnected by a network for transferring messages among the processors. At least one processor generates messages of a configuration type. The network comprises a plurality of nodes interconnected in a tree pattern in a series of levels from a lower leaf level to an upper physical root level, with the leaf nodes connected to the processors. Each of the nodes includes a root flag that can be set or cleared in response to a message of the configuration type to establish the node as a logical root. For each node, if the node is a logical root it transfers messages received from a node at a lower level in the tree back down the tree, but if the node is not a logical root it transfers messages received at a lower level node to a higher level node.

摘要翻译： 一种数字计算机，包括由网络互连以在处理器之间传送消息的多个处理器。 至少一个处理器生成配置类型的消息。 该网络包括多个节点，其以树形图案从下叶级别到上层物理根级别的一系列级别互连，叶节点连接到处理器。 每个节点包括可以响应于配置类型的消息来建立该节点作为逻辑根而设置或清除的根标志。 对于每个节点，如果节点是逻辑根，则将从树中的较低级别的节点接收的消息从树中向下传播，但是如果节点不是逻辑根，则将在较低级节点处接收的消息传送到 高级节点。

公开(公告)号：US5842026A

公开(公告)日：1998-11-24

申请号：US672947

申请日：1996-07-01

申请人： Monica C. Wong-Chan ,  Erik Hagersten

发明人： Monica C. Wong-Chan ,  Erik Hagersten

IPC分类号： G06F15/16 ,  G06F9/48 ,  G06F15/177 ,  G06F13/24

CPC分类号： G06F9/4812

摘要： An interrupt mechanism handles an interrupt transaction between a source processor and a target processor on separate nodes in a multi-processor system. The nodes are connected to a network through node interface controls between the node and the network. The transaction begins by initiating the interrupt transaction at the source processor. The interrupt mechanism detects if the target processor is at a remote node on a system bus across the network, and if it is the mechanism sends an ignore signal to the source processor. Then the mechanism suspends the interrupt transaction at the source processor if it detects the target processor is at a remote node. The mechanism performs an ACK/NACK (acknowledge/non-acknowledge) operation at the target processor and returning an ACK signal or a NACK signal to the source processor across the network. This ACK/NACK signal wakes-up the source processor. The source processor sends interrupt data to the target processor if an ACK signal is received and aborts the interrupt transaction if a NACK signal is received.

摘要翻译： 中断机制处理多处理器系统中单独节点上的源处理器和目标处理器之间的中断事务。 节点通过节点和网络之间的节点接口控制连接到网络。 事务从源处理器启动中断事务开始。 中断机制检测目标处理器是否位于跨网络的系统总线上的远程节点，如果机制是向源处理器发送忽略信号。 那么如果检测到目标处理器在远程节点处，则该机制将在源处理器处挂起中断事务。 该机制在目标处理器处执行ACK / NACK（确认/非确认）操作，并通过网络将ACK信号或NACK信号返回给源处理器。 该ACK / NACK信号唤醒源处理器。 如果接收到ACK信号，则源处理器向目标处理器发送中断数据，并且如果接收到NACK信号则中断事务。

公开(公告)号：US06219775B1

公开(公告)日：2001-04-17

申请号：US09040747

申请日：1998-03-18

申请人： Jon P. Wade ,  Daniel R. Cassiday ,  Robert D. Lordi ,  Guy Lewis Steele, Jr. ,  Margaret A. St. Pierre ,  Monica C. Wong-Chan ,  Zahi S. Abuhamdeh ,  David C. Douglas ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  W. Daniel Hillis ,  Scott J. Smith ,  Shaw-Wen Yang ,  Robert C. Zak, Jr.

发明人： Jon P. Wade ,  Daniel R. Cassiday ,  Robert D. Lordi ,  Guy Lewis Steele, Jr. ,  Margaret A. St. Pierre ,  Monica C. Wong-Chan ,  Zahi S. Abuhamdeh ,  David C. Douglas ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  W. Daniel Hillis ,  Scott J. Smith ,  Shaw-Wen Yang ,  Robert C. Zak, Jr.

IPC分类号： G06F702

CPC分类号： G06F15/8092 ,  G06F15/17381 ,  G06F15/8084 ,  G06F21/52

摘要： A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.

摘要翻译： 大型并行计算机包括多个处理节点和由网络互连的至少一个控制节点。 该网络便于处理节点之间的数据传输和从控制节点到处理节点的命令。 每个处理节点包括用于在网络上传输数据并从其接收数据和命令的接口，用于存储数据的至少一个存储器模块，节点处理器和辅助处理器。 节点处理器在产生存储器访问请求的过程中接收由接口接收的命令并响应于此处理数据，以便于从存储器模块中的数据检索或存储数据。 节点处理器进一步通过接口控制网络上的数据传输。 辅助处理器连接到存储器模块和节点处理器。 响应于来自节点处理器的存储器访问请求，辅助处理器执行存储器访问操作以将从节点处理器接收的数据存储在存储器模块中，或者从存储器模块检索数据以传送到节点处理器。 响应于来自节点处理器的辅助处理指令，辅助处理器结合存储器模块中的数据执行数据处理操作。

公开(公告)号：US5872987A

公开(公告)日：1999-02-16

申请号：US714635

申请日：1996-09-16

申请人： Jon P. Wade ,  Daniel R. Cassiday ,  Robert D. Lordi ,  Guy Lewis Steele, Jr. ,  Margaret A. St. Pierre ,  Monica C. Wong-Chan ,  Zahi S. Abuhamdeh ,  David C. Douglas ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  W. Daniel Hillis ,  Scott J. Smith ,  Shaw-Wen Yang ,  Robert C. Zak, Jr.

发明人： Jon P. Wade ,  Daniel R. Cassiday ,  Robert D. Lordi ,  Guy Lewis Steele, Jr. ,  Margaret A. St. Pierre ,  Monica C. Wong-Chan ,  Zahi S. Abuhamdeh ,  David C. Douglas ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  W. Daniel Hillis ,  Scott J. Smith ,  Shaw-Wen Yang ,  Robert C. Zak, Jr.

IPC分类号： G06F15/173 ,  G06F15/78 ,  G06F15/80 ,  G06F7/02

CPC分类号： G06F15/8092 ,  G06F15/17381 ,  G06F15/8084 ,  G06F21/52

摘要： A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.

摘要翻译： 大型并行计算机包括多个处理节点和由网络互连的至少一个控制节点。 该网络便于处理节点之间的数据传输和从控制节点到处理节点的命令。 每个处理节点包括用于从网络传输数据并从其接收数据和命令的接口，用于存储数据的至少一个存储器模块，节点处理器和辅助处理器。 节点处理器在产生存储器访问请求的过程中接收由接口接收的命令并响应于此处理数据，以便于从存储器模块中的数据检索或存储数据。 节点处理器进一步通过接口控制网络上的数据传输。 辅助处理器连接到存储器模块和节点处理器。 响应于来自节点处理器的存储器访问请求，辅助处理器执行存储器访问操作以将从节点处理器接收的数据存储在存储器模块中，或者从存储器模块检索数据以传送到节点处理器。 响应于来自节点处理器的辅助处理指令，辅助处理器结合存储器模块中的数据执行数据处理操作。