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    Chisels and procedure for insertion of spinal implant in a spinal disc space
    3.
    发明申请
    Chisels and procedure for insertion of spinal implant in a spinal disc space 有权
    将脊柱植入物插入椎间盘空间的凿子和程序

    公开(公告)号：US20050251146A1

    公开(公告)日：2005-11-10

    申请号：US10520794

    申请日：2003-07-16

    申请人： Erik Martz ,  David Chow

    发明人： Erik Martz ,  David Chow

    IPC分类号： A61B17/16 ,  A61F2/00 ,  A61F2/28 ,  A61F2/44 ,  A61F2/46

    CPC分类号： A61F2/4684 ,  A61B17/1604 ,  A61B17/1671 ,  A61F2/28 ,  A61F2/4455 ,  A61F2002/30131 ,  A61F2002/448 ,  A61F2230/0013 ,  A61F2310/00359

    摘要： A chisel with U.V-shaped, saw tooth or other shaped opposing blades is used to form channels in adjacent vertebrae. The chisel has a projection extending from at least one of the top and bottom surfaces to limit depth of penetration into the vertebrae. A guide member may be attached to the forward tip of the chisel to guide the chisel into the disc space to uniformly chisel both adjacent vertebrae simultaneously to form a channel in the vertebrae. The so formed channels serve as sa guide for a second chisel having no guide member. The second chisel, which may be a box chisel, is used to complete the channels to the desired depth to receive an associated implant, typically of cortical bone. Other embodiments are disclosed in which a two step box chisel has a retractable guide member for initially guiding the chisel as it forms partial channels in the vertebrae disc space. The guide member is then retracted and the channels formed to the desired depth. The chisels include guide member pins which serve to both limit the extension and retraction of the guide member and also to serve to limit the depth of penetration of the chisel, physically and visually. The guide member may be retracted with a rotatable knob and a threaded engaged rod or with an axially displaceable pin and rod assembly attached to the guide member. A procedure for using the chisels is also disclosed.

    摘要翻译： 使用具有U.V形锯齿或其他形状相对的刀片的凿子在相邻椎骨中形成通道。 凿子具有从顶表面和底表面中的至少一个延伸的突起，以限制穿入椎骨的深度。 引导构件可以附接到凿子的前端，以将凿子引导到椎间盘空间中，以均匀地同时凿孔两个相邻的椎骨以在椎骨中形成通道。 这样形成的通道用作没有引导构件的第二凿子的引导件。 可以使用第二凿子，其可以是盒式凿子，以将通道完成到期望的深度以接收通常为皮层骨的相关植入物。 公开了其他实施例，其中两台凿子具有可缩回的引导构件，用于在椎骨盘空间中形成部分通道时最初引导凿子。 然后引导构件缩回并且通道形成到期望的深度。 凿子包括引导构件销，其用于限制引导构件的延伸和缩回，并且还用于在物理和视觉上限制凿子的穿透深度。 引导构件可以用可旋转的旋钮和螺纹接合的杆或与安装在引导构件上的可轴向移位的销和杆组件缩回。 还公开了使用凿子的方法。

    Adjustable instrumentation for spinal implant insertion
    4.
    发明申请
    Adjustable instrumentation for spinal implant insertion 有权
    用于脊柱植入物插入的可调节仪器

    公开(公告)号：US20060095043A1

    公开(公告)日：2006-05-04

    申请号：US11253410

    申请日：2005-10-19

    申请人： Erik Martz ,  Jo-Wen Lin ,  David Chow ,  Daniel Rosenthal

    发明人： Erik Martz ,  Jo-Wen Lin ,  David Chow ,  Daniel Rosenthal

    IPC分类号： A61B17/58

    CPC分类号： A61F2/4611 ,  A61B17/1604 ,  A61B17/1606 ,  A61B17/1659 ,  A61B17/1671 ,  A61B17/320016 ,  A61B90/50 ,  A61B2017/00261 ,  A61B2017/00464 ,  A61B2017/0256 ,  A61B2017/2904 ,  A61B2017/2931 ,  A61F2/442 ,  A61F2/4455 ,  A61F2002/30538 ,  A61F2002/30795 ,  A61F2002/4624 ,  A61F2002/4627 ,  A61F2002/4628 ,  A61F2002/4629 ,  A61F2002/4679 ,  A61F2250/0006

    摘要： A plurality of differently configured bone spinal implants for insertion in a spine have a cylindrical bore for receiving an insertion head stud. A plurality of instruments are disclosed each of which have a first connection element which is either a male or female member such as e.g., a ball and socket, a cylinder and socket and so on for forming either a stationary or articulating interchangeable joint for a plurality of disc processing heads or implant insertion heads. The plurality of disc space processing heads or implant insertion heads have a complementary second joint member for interchangeable attachment to the first connection element. The implant insertion heads or disc processing heads have different configurations for different shaped implants. Different instrument insertion or disc processing heads such as implant inserters, impactors, rasps, distractors, curettes, rongeur, and so on are disclosed as being interchangeable with a common instrument in which articulating or fixed joints are provided the interchangeable heads.

    摘要翻译： 用于插入脊椎的多个不同构造的骨脊椎植入物具有用于接收插入头钉的圆柱形孔。 公开了多个仪器，每个仪器具有第一连接元件，该第一连接元件是阳或阴构件，例如球窝，气缸和插座等，用于形成用于多个的静止或可铰接的可互换接头 的盘处理头或植入物插入头。 多个盘空间处理头或植入物插入头具有用于可互换连接到第一连接元件的互补的第二关节构件。 植入物插入头或椎间盘处理头具有不同形状的植入物的不同构型。 公开了不同的仪器插入或盘处理头，例如植入物插入器，冲击器，锉刀，牵引器，刮刀，护腿等，其可与可互换的头部提供关节或固定接头的通用仪器互换。

    Method and device for growing pseudomorphic AlInAsSb on InAs
    6.
    发明授权
    Method and device for growing pseudomorphic AlInAsSb on InAs 失效
    用于在InAs上生长伪晶AlInAsSb的方法和装置

    公开(公告)号：US07968435B1

    公开(公告)日：2011-06-28

    申请号：US12491004

    申请日：2009-06-24

    申请人： Peter Deelman ,  Ken Elliott ,  David Chow

    发明人： Peter Deelman ,  Ken Elliott ,  David Chow

    IPC分类号： H01L21/20

    CPC分类号： H01L21/02395 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02631

    摘要： A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.

    摘要翻译： 正在公开半导体器件和方法。 半导体器件公开了InAs层，由InAs层支撑的多个III-V族三元层和由InAs层支撑的多个III-V族第三层，其中III-V族三元层与 彼此由一个III-V组单独的三层组成。 该方法公开了提供InAs层，生长多个III-V族三元层，并生长多个III-V族第三层，其中III-V族三元层通过单组III- V第三层，并由InAs层支持。

    Method and device for growing pseudomorphic AlInAsSb on InAs
    7.
    发明授权
    Method and device for growing pseudomorphic AlInAsSb on InAs 失效
    用于在InAs上生长伪晶AlInAsSb的方法和装置

    公开(公告)号：US07598158B1

    公开(公告)日：2009-10-06

    申请号：US11447338

    申请日：2006-06-05

    申请人： Peter Deelman ,  Ken Elliott ,  David Chow

    发明人： Peter Deelman ,  Ken Elliott ,  David Chow

    IPC分类号： H01L21/20

    CPC分类号： H01L21/02395 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02631

    摘要： A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.

    摘要翻译： 正在公开半导体器件和方法。 半导体器件公开了InAs层，由InAs层支撑的多个III-V族三元层和由InAs层支撑的多个III-V族第三层，其中III-V族三元层与 彼此由一个III-V组单独的三层组成。 该方法公开了提供InAs层，生长多个III-V族三元层，并生长多个III-V族第三层，其中III-V族三元层通过单组III- V第三层，并由InAs层支持。

    System and method for producing high volume flash memory cards
    8.
    发明申请
    System and method for producing high volume flash memory cards 审中-公开
    用于生产大容量闪存卡的系统和方法

    公开(公告)号：US20080065788A1

    公开(公告)日：2008-03-13

    申请号：US11979102

    申请日：2007-10-31

    申请人： David Chow ,  Sidney Young ,  Frank Yu ,  Abraham Ma ,  Ming-Shiang Shen

    发明人： David Chow ,  Sidney Young ,  Frank Yu ,  Abraham Ma ,  Ming-Shiang Shen

    IPC分类号： G06F13/10

    CPC分类号： G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G07C9/00087 ,  G07C2009/00095 ,  H01R13/629

    摘要： A system for producing high volume flash memory cards includes a processing unit, a PC interface for connecting to an external PC, a PC drive circuit connected to the PC interface and the processing unit, a card interface for connecting to an external flash memory card, and a card drive circuit connected to the card interface and the processing unit. The PC drive circuit realizes communication between the PC and the processing unit. The card drive circuit realizes communication between the flash memory card and the processing unit. The processing unit receives command or data from the PC interface, and sends card re-initialization command or data to the flash memory card via the card interface.

    摘要翻译： 一种用于生产大容量闪存卡的系统包括处理单元，用于连接到外部PC的PC接口，连接到PC接口的PC驱动电路和处理单元，用于连接到外部闪存卡的卡接口， 以及连接到卡接口和处理单元的卡驱动电路。 PC驱动电路实现PC与处理单元之间的通信。 卡驱动电路实现闪存卡和处理单元之间的通信。 处理单元从PC接口接收命令或数据，并通过卡接口将卡重新初始化命令或数据发送到闪存卡。

    Multi-Channel Flash Module with Plane-Interleaved Sequential ECC Writes and Background Recycling to Restricted-Write Flash Chips
    9.
    发明申请
    Multi-Channel Flash Module with Plane-Interleaved Sequential ECC Writes and Background Recycling to Restricted-Write Flash Chips 有权
    具有平面交错顺序ECC的多通道闪存模块写入和背景回收限制写入闪存芯片

    公开(公告)号：US20080034154A1

    公开(公告)日：2008-02-07

    申请号：US11871627

    申请日：2007-10-12

    申请人： Charles Lee ,  Abraham Ma ,  Frank Yu ,  David Chow ,  Ming-Shiang Shen

    发明人： Charles Lee ,  Abraham Ma ,  Frank Yu ,  David Chow ,  Ming-Shiang Shen

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0607 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C16/0408 ,  G11C2211/5649

    摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.

    摘要翻译： 使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。 这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。 物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。 这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 还执行后台回收和ECC写入。

    Flash Module with Plane-Interleaved Sequential Writes to Restricted-Write Flash Chips
    10.
    发明申请
    Flash Module with Plane-Interleaved Sequential Writes to Restricted-Write Flash Chips 有权
    闪存模块与平面交错顺序写入限制写入闪存芯片

    公开(公告)号：US20080034153A1

    公开(公告)日：2008-02-07

    申请号：US11871011

    申请日：2007-10-11

    申请人： Charles Lee ,  Frank Yu ,  Abraham Ma ,  David Chow ,  Ming-Shiang Shen

    发明人： Charles Lee ,  Frank Yu ,  Abraham Ma ,  David Chow ,  Ming-Shiang Shen

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F12/0607 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C11/5621 ,  G11C16/0408

    摘要： A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.

    摘要翻译： PCIE总线上的闪存控制器控制闪存总线上的闪存模块。 闪存模块使用从逻辑块索引的最低位提取的交错比特进行平面交织。 这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。 物理顺序地址计数器通过在中间物理块比特之前递增平面交织比特，然后将MSB重新定位到中间物理块比特之上来生成物理块号。 这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 RAM物理页有效表跟踪四个平面中的有效页面，而RAM映射表存储由物理顺序地址计数器生成的逻辑扇区的平面，块和页面地址。