公开(公告)号：US4259654A

公开(公告)日：1981-03-31

申请号：US34508

申请日：1979-04-30

申请人： Erik Persson ,  Johnny Sundin

发明人： Erik Persson ,  Johnny Sundin

IPC分类号： H01F27/36 ,  H01F15/04

CPC分类号： H01F27/367

摘要： Disclosed are improved constructions for power transformers and reactors having windings of tape-formed conductor material which tend to reduce additional losses in the windings. In the improved construction for a power transformer or reactor comprising a core containing magnetic material and having legs and a yoke and comprising windings including a tape-formed conductor material arranged concentrically around the core legs, the innermost of the windings has a first portion located nearest the core leg which has an axial length greater than the length of the portion of the winding located radially outside said first portion. The first portion thereby forms a cylindrical shield for controlling the magnetic leakage flux appearing outside the ends of the winding.

摘要翻译： 公开了用于电力变压器和反应器的改进的结构，其具有带状导体材料的绕组，其倾向于减少绕组中的额外损耗。 在用于电力变压器或电抗器的改进的结构中，该电力变压器或电抗器包括一个包含磁性材料并且具有支脚和磁轭的磁芯，并且包括绕组，该绕组包括围绕芯柱同心布置的带状导体材料，最里面的绕组具有位于最近的第一部分 所述芯腿的轴向长度大于位于所述第一部分径向外侧的所述绕组部分的长度。 第一部分由此形成用于控制出现在绕组末端外部的磁漏磁通的圆柱形屏蔽。

公开(公告)号：US08660173B2

公开(公告)日：2014-02-25

申请号：US12923797

申请日：2010-10-07

申请人： Andreas Björklund ,  Erik Persson ,  Pontus Borg ,  Mats Petter Wallander

发明人： Andreas Björklund ,  Erik Persson ,  Pontus Borg ,  Mats Petter Wallander

IPC分类号： H04B1/66

CPC分类号： H04N19/423 ,  H04N19/61

摘要： A video data processing apparatus is provided comprising processing circuitry for performing video processing operations requiring access to video reference frames, and a memory management unit configured to translate virtual addresses into physical addresses. Translation circuitry is provided responsive to a memory access request for reference frame pixel data issued by the processing circuitry to perform a translation process on video reference frame information such that the set of input values for at least one hash function in the memory management unit comprises video reference frame identifier bits contained with the video reference frame information. This approach has been found to reduce the frequency of aliasing in the memory management unit when retrieving video reference frames.

摘要翻译： 提供了一种视频数据处理装置，包括用于执行需要访问视频参考帧的视频处理操作的处理电路，以及被配置为将虚拟地址转换成物理地址的存储器管理单元。 提供翻译电路，其响应于由处理电路发出的参考帧像素数据的存储器访问请求，以执行对视频参考帧信息的转换处理，使得存储器管理单元中的至少一个散列函数的输入值集合包括视频 包含在视频参考帧信息中的参考帧标识符位。 已经发现这种方法在检索视频参考帧时降低存储器管理单元中的混叠频率。

公开(公告)号：US08532192B2

公开(公告)日：2013-09-10

申请号：US12805149

申请日：2010-07-14

申请人： Erik Persson ,  Tomas Edsö

发明人： Erik Persson ,  Tomas Edsö

IPC分类号： H04N11/02 ,  H04N11/04 ,  H04N7/12 ,  H04N7/32

CPC分类号： H04N19/517 ,  H04N19/428 ,  H04N19/43 ,  H04N19/436 ,  H04N19/44 ,  H04N19/48 ,  H04N19/61 ,  H04N19/91

摘要： A video processing apparatus and method are provided, the video processing apparatus comprising first stage video processing circuitry and second stage video processing circuitry. The first stage video processing circuitry receives input video data and performs one or more processing operations on the input video data to generate an intermediate representation of the input video data. The intermediate representation comprises first and second separate data portions, with the first data portion containing transient data derived from the input video data and the second data portion containing long term data derived from the input video data. Transient data is only required for processing of a single video frame, while the long term data is required for processing of at least two video frames. The first stage video processing circuitry is arranged to output the first and second separate data portions for storing in a buffer, and the second stage video processing circuitry then retrieves the first and second data portions from the buffer and performs one or more further processing operations on those data portions in order to generate output video data. The transient data is compressed prior to being stored in the buffer, and then decompressed when retrieved from the buffer by the second stage video processing circuitry. Such an approach enables the operations of the second stage video processing circuitry to be decoupled from the operations of the first stage video processing circuitry, while reducing the storage capacity requirements of the buffer.

摘要翻译： 提供一种视频处理装置和方法，该视频处理装置包括第一级视频处理电路和第二级视频处理电路。 第一级视频处理电路接收输入视频数据并对输入视频数据执行一个或多个处理操作，以产生输入视频数据的中间表示。 中间表示包括第一和第二分离数据部分，第一数据部分包含从输入视频数据导出的瞬态数据，第二数据部分包含从输入视频数据导出的长期数据。 只需要处理单个视频帧的瞬态数据，而处理至少两个视频帧需要长期数据。 第一级视频处理电路被布置为输出用于存储在缓冲器中的第一和第二分离数据部分，然后第二级视频处理电路从缓冲器中检索第一和第二数据部分，并执行一个或多个进一步的处理操作 这些数据部分以产生输出视频数据。 瞬态数据在被存储在缓冲器中之前被压缩，然后在由第二级视频处理电路从缓冲器检索时被解压缩。 这种方法使得第二级视频处理电路的操作能够与第一级视频处理电路的操作分离，同时减少缓冲器的存储容量需求。

公开(公告)号：US20120169936A1

公开(公告)日：2012-07-05

申请号：US12929137

申请日：2011-01-03

申请人： Erik Persson ,  Per Edgren

发明人： Erik Persson ,  Per Edgren

IPC分类号： H04N5/21

CPC分类号： H04N5/21 ,  H04N9/646 ,  H04N9/77

摘要： The present invention provides filter circuitry for reducing noise in an input stream of image signals having luminance and chrominance components. Spatial filter circuitry is provided which, for a current image signal of the input stream, generates a spatially filtered internal signal from at least the luminance component of the current image signal. Comparison circuitry is configured to compare the current image signal with temporal data derived from multiple image signals of the input stream, and to generate a control signal dependent on the comparison. Combining circuitry is then used to combine, in a ratio determined by the control signal, the spatially filtered internal signal with at least a luminance component derived from the temporal data, in order to generate at least the luminance component of a current output image signal that forms a noise reduced version of the current image signal. Such a form of filter circuitry has been found to provide a filtered stream of image signals with significant noise suppression, and is particularly well suited to providing a filtered stream of image signals for input to video encoding circuitry, enabling significant improvements in the efficiency of the encoding circuitry by virtue of the manner in which the noise is suppressed.

摘要翻译： 本发明提供了用于降低具有亮度和色度分量的图像信号的输入流中的噪声的滤波器电路。 提供空间滤波器电路，对于输入流的当前图像信号，至少从当前图像信号的亮度分量产生空间滤波的内部信号。 比较电路被配置为将当前图像信号与从输入流的多个图像信号导出的时间数据进行比较，并且根据比较产生控制信号。 然后，组合电路用于以由控制信号确定的比例将至少由时间数据导出的亮度分量的空间滤波内部信号组合起来，以至少产生当前输出图像信号的亮度分量， 形成当前图像信号的降噪版本。 已经发现这种形式的滤波器电路提供具有显着噪声抑制的经过滤波的图像信号流，并且特别适合于提供用于输入到视频编码电路的经过滤波的图像信号流，使得能够显着提高 通过抑制噪声的方式进行编码电路。

公开(公告)号：US20110087858A1

公开(公告)日：2011-04-14

申请号：US12588263

申请日：2009-10-08

申请人： Erik Persson ,  Ola Hugosson ,  Andreas Björklund

发明人： Erik Persson ,  Ola Hugosson ,  Andreas Björklund

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/1018 ,  G06F12/1027 ,  G06F12/122

摘要： A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.

摘要翻译： 提供了一种数据处理装置，包括被配置为发布包括虚拟地址的存储器访问请求的多个主设备。 存储器管理单元被配置为接收存储器访问请求并将包括在存储器访问请求中的虚拟地址从请求主设备转换成指示存储器中的存储位置的物理地址。 存储器管理单元具有内部存储单元，其具有多个条目，其中存储对应的虚拟地址部分和物理地址部分的指示。 存储器管理单元被配置为根据虚拟地址和请求主设备的标识符来选择内部存储单元的条目。 因此避免了主设备在使用内部存储单元时的冲突。

公开(公告)号：US08773593B2

公开(公告)日：2014-07-08

申请号：US12929137

申请日：2011-01-03

申请人： Erik Persson ,  Per Edgren

发明人： Erik Persson ,  Per Edgren

IPC分类号： H04N5/21

CPC分类号： H04N5/21 ,  H04N9/646 ,  H04N9/77

摘要： The present invention provides filter circuitry for reducing noise in an input stream of image signals having luminance and chrominance components. Spatial filter circuitry is provided which, for a current image signal of the input stream, generates a spatially filtered internal signal from at least the luminance component of the current image signal. Comparison circuitry is configured to compare the current image signal with temporal data derived from multiple image signals of the input stream, and to generate a control signal dependent on the comparison. Combining circuitry is then used to combine, in a ratio determined by the control signal, the spatially filtered internal signal with at least a luminance component derived from the temporal data, in order to generate at least the luminance component of a current output image signal that forms a noise reduced version of the current image signal. Such a form of filter circuitry has been found to provide a filtered stream of image signals with significant noise suppression, and is particularly well suited to providing a filtered stream of image signals for input to video encoding circuitry, enabling significant improvements in the efficiency of the encoding circuitry by virtue of the manner in which the noise is suppressed.

摘要翻译： 本发明提供了用于降低具有亮度和色度分量的图像信号的输入流中的噪声的滤波器电路。 提供空间滤波器电路，对于输入流的当前图像信号，至少从当前图像信号的亮度分量产生空间滤波的内部信号。 比较电路被配置为将当前图像信号与从输入流的多个图像信号导出的时间数据进行比较，并且根据比较产生控制信号。 然后，组合电路用于以由控制信号确定的比例将至少由时间数据导出的亮度分量的空间滤波内部信号组合起来，以至少产生当前输出图像信号的亮度分量， 形成当前图像信号的降噪版本。 已经发现这种形式的滤波器电路提供具有显着噪声抑制的经过滤波的图像信号流，并且特别适合于提供用于输入到视频编码电路的经过滤波的图像信号流，使得能够显着提高 通过抑制噪声的方式进行编码电路。

公开(公告)号：US20100313060A1

公开(公告)日：2010-12-09

申请号：US12656156

申请日：2010-01-19

申请人： Andreas Björklund ,  Erik Persson ,  Ola Hugosson

发明人： Andreas Björklund ,  Erik Persson ,  Ola Hugosson

IPC分类号： G06F15/76 ,  G06F9/06 ,  G06F1/04

CPC分类号： G06F9/30141 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3826 ,  G06F9/3836

摘要： A data processing apparatus and method are provided for performing a predetermined rearrangement operation. The data processing apparatus comprises a vector register bank having a plurality of vector registers, with each vector register comprising a plurality of storage cells such that the plurality of vector registers provide a matrix of storage cells. Each storage cell is arranged to store a data element. A vector processing unit is provided for executing a sequence of vector instructions in order to apply operations to the data elements held in the vector register bank. Responsive to a vector matrix rearrangement instruction specifying a predetermined rearrangement operation to be performed on the data elements in the matrix of storage cells, the vector processing unit is arranged to issue a set rearrangement enable signal to the vector register bank. The write interface of the vector register bank is modified to provide not only a first input for receiving the data elements generated by the vector processing unit during normal execution, but also has a second input coupled via a data rearrangement path to the matrix of storage cells via which the data elements currently stored in the matrix of storage cells are provided to the write interface in a rearranged form representing the arrangement of data elements that would be obtained by performance of the predetermined rearrangement operation. When the rearrangement enable signal is set, the write interface then performs a write operation to the storage cells of the matrix using the data elements received at the second input. This enables the predetermined rearrangement operation to be performed at high speed and with significantly less complexity than in prior art systems.

摘要翻译： 提供了一种用于执行预定重排动作的数据处理装置和方法。 数据处理装置包括具有多个向量寄存器的向量寄存器组，每个向量寄存器包括多个存储单元，使得多个向量寄存器提供存储单元矩阵。 每个存储单元被布置成存储数据元素。 向量处理单元被提供用于执行向量指令序列，以便将操作应用于保持在向量寄存器组中的数据元素。 响应于指定对存储单元矩阵中的数据元素执行的预定重排操作的向量矩阵重排指令，向量处理单元被布置为向向量寄存器组发出置位重排使能信号。 修改向量寄存器组的写接口，不仅提供用于在正常执行期间接收由向量处理单元生成的数据元素的第一输入，还具有经由数据重排路径耦合到存储单元矩阵的第二输入 通过其将当前存储在存储单元的矩阵中的数据元素以重新排列的形式提供给写入接口，表示通过执行预定重新排列操作将获得的数据元素的布置。 当重新布置使能信号被设置时，写入接口然后使用在第二输入端接收到的数据元素对矩阵的存储单元进行写入操作。 这使得能够以比现有技术的系统更高的速度和更小的复杂度执行预定的重新排列操作。

公开(公告)号：US4819184A

公开(公告)日：1989-04-04

申请号：US102516

申请日：1987-09-29

申请人： Sven Jonsson ,  Erik Persson ,  Lars stlund

发明人： Sven Jonsson ,  Erik Persson ,  Lars stlund

IPC分类号： B25J9/18 ,  G05B19/37 ,  G05B13/00

CPC分类号： G05B19/373

摘要： An industrial robot has a position controller for each one of the axes of the robot and a computer for control of the robot. The computer continuously determines, with the aid of a mathematical model set up in advance, in dependence on the robot configuration and load in question, the mass moment of inertia of the axes, the coupled mass moment of inertia, and the moment caused by gravity. From the relationships between acceleration/deceleration and the drive motor torque for the different axes, the maximum available acceleration/deceleration for the axis is determined while assuming that maximum motor torque prevails for each axis. For each axis this value is compared with the maximum acceleration/deceleration value that may be allowed from the point of view of stability. On the basis of the lower of these values, optimum gain is determined and set in the position controller and/or a path planning parameter.

公开(公告)号：US08924686B2

公开(公告)日：2014-12-30

申请号：US12588263

申请日：2009-10-08

申请人： Erik Persson ,  Ola Hugosson ,  Andreas Björklund

发明人： Erik Persson ,  Ola Hugosson ,  Andreas Björklund

IPC分类号： G06F12/00 ,  G06F9/26 ,  G06F9/34 ,  G06F12/10

CPC分类号： G06F12/1018 ,  G06F12/1027 ,  G06F12/122

摘要： A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.

摘要翻译： 提供了一种数据处理装置，包括被配置为发布包括虚拟地址的存储器访问请求的多个主设备。 存储器管理单元被配置为接收存储器访问请求并将包括在存储器访问请求中的虚拟地址从请求主设备转换成指示存储器中的存储位置的物理地址。 存储器管理单元具有内部存储单元，其具有多个条目，其中存储对应的虚拟地址部分和物理地址部分的指示。 存储器管理单元被配置为根据虚拟地址和请求主设备的标识符来选择内部存储单元的条目。 因此避免了主设备在使用内部存储单元时的冲突。

公开(公告)号：US08661225B2

公开(公告)日：2014-02-25

申请号：US12656152

申请日：2010-01-19

申请人： Andreas Björklund ,  Erik Persson ,  Ola Hugosson

发明人： Andreas Björklund ,  Erik Persson ,  Ola Hugosson

IPC分类号： G06F15/00

CPC分类号： G06F9/30072 ,  G06F9/30036 ,  G06F9/30069 ,  G06F9/3887

摘要： A data processing apparatus and method and provided for handling vector instructions. The data processing apparatus has a register data store with a plurality of registers arranged to store data elements. A vector processing unit is then used to execute a sequence of vector instructions, with the vector processing unit having a plurality of lanes of parallel processing and having access to the register data store in order to read data elements from, and write data elements to, the register data store during the execution of the sequence of vector instructions. A skip indication storage maintains a skip indicator for each of the lanes of parallel processing. The vector processing unit is responsive to a vector skip instruction to perform an update operation to set within the skip indication storage the skip indicator for a determined one or more lanes. The vector processing unit is responsive to a vector operation instruction to perform an operation in parallel on data elements input to the plurality of lanes of parallel processing, but to exclude from the performance of the operation any lane whose associated skip indicator is set. This allows the operation specified by vector instructions to be performed conditionally within each of the lanes of parallel processing without any modification to the vector instructions that are specifying those operations.

摘要翻译： 一种用于处理向量指令的数据处理装置和方法。 数据处理装置具有寄存器数据存储器，其具有多个用于存储数据元素的寄存器。 然后，矢量处理单元用于执行矢量指令序列，其中矢量处理单元具有多个并行处理通道，并且能够访问寄存器数据存储器，以便从数据元素读取数据元素， 在执行向量指令序列期间的寄存器数据存储。 跳过指示存储保持每个并行处理通道的跳过指示符。 向量处理单元响应于向量跳过指令执行更新操作，以在跳过指示存储内设置用于所确定的一个或多个车道的跳过指示符。 向量处理单元响应于矢量操作指令，并行地对输入到多个并行处理通道的数据元素执行操作，但是从执行操作排除任何相关联的跳过指示符被设置的通道。 这允许在并行处理的每个通道内有条件地执行由向量指令指定的操作，而不对指定这些操作的向量指令进行任何修改。