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    METHOD AND SYSTEM FOR EVALUATING LINK-HOSTING WEBPAGES
    1.
    发明申请
    METHOD AND SYSTEM FOR EVALUATING LINK-HOSTING WEBPAGES 审中-公开
    用于评估链接主体的方法和系统

    公开(公告)号：US20120066359A1

    公开(公告)日：2012-03-15

    申请号：US12878490

    申请日：2010-09-09

    申请人： Erik S. Freeman ,  Carl A. Dunham ,  Autumn Francesca ,  Richard Egan ,  Patrick S. Wynne ,  David Counts ,  Edward M. Ives ,  Bradd Libby

    发明人： Erik S. Freeman ,  Carl A. Dunham ,  Autumn Francesca ,  Richard Egan ,  Patrick S. Wynne ,  David Counts ,  Edward M. Ives ,  Bradd Libby

    IPC分类号： G06F15/173

    CPC分类号： G06Q30/0256 ,  G06F16/951

    摘要： A method for valuing a link-hosting webpage is provided. The method includes the act of receiving, on a computer system, at least one keyword. The method also includes the act of receiving, on a computer system, at least one identifier of a webpage, the webpage having been previously identified as a link-hosting webpage. The method also includes the act of accessing information about the webpage over a computer network. The method also includes the act of determining an importance of the webpage based on the at least one keyword and the information about the webpage. The method also includes the act of displaying the importance on a computer-based user interface.

    摘要翻译： 提供了一种用于评估链接主机网页的方法。 该方法包括在计算机系统上接收至少一个关键字的动作。 该方法还包括在计算机系统上接收网页的至少一个标识符的动作，该网页先前被识别为链接主机网页。 该方法还包括通过计算机网络访问关于网页的信息的动作。 该方法还包括基于至少一个关键字和关于网页的信息确定网页的重要性的动作。 该方法还包括在基于计算机的用户界面上显示重要性的动作。

    Component testing and recovery
    2.
    发明申请
    Component testing and recovery 有权
    组件测试和恢复

    公开(公告)号：US20070094555A1

    公开(公告)日：2007-04-26

    申请号：US11258484

    申请日：2005-10-24

    申请人： Adrian Ong ,  Richard Egan

    发明人： Adrian Ong ,  Richard Egan

    IPC分类号： G11C29/00

    CPC分类号： G11C29/846 ,  G11C29/56 ,  G11C29/76 ,  G11C29/81 ,  G11C2229/743 ,  G11C2229/763

    摘要： Disclosed are systems and methods of producing electronic devices. These electronic devices include excess circuits to be used as replacements for circuits that are found to be defective within the electronic device. The excess circuits are included in a different device component than the circuits that are found to be defective. The replacement process occurs after the excess circuits and defective circuits are included in an electronic device including the different device components. Identification of the defective circuits may occur before or after the defective circuits are incorporated in the electronic device. In some embodiments, systems and methods of the invention result in improved manufacturing yields as compared with the prior art.

    摘要翻译： 公开了制造电子设备的系统和方法。 这些电子设备包括用作电子设备中发现有缺陷的电路的替代物的多余电路。 多余电路被包含在与发现有缺陷的电路不同的器件部件中。 替换处理发生在多余电路和故障电路包括在包括不同器件组件的电子设备中之后。 有缺陷的电路的识别可能发生在电路装置内的故障电路之前或之后。 在一些实施例中，与现有技术相比，本发明的系统和方法导致改进的制造产量。

    Printer color registration correction
    3.
    发明申请
    Printer color registration correction 有权
    打印机颜色注册更正

    公开(公告)号：US20050093956A1

    公开(公告)日：2005-05-05

    申请号：US10698209

    申请日：2003-10-31

    申请人： Richard Egan

    发明人： Richard Egan

    IPC分类号： H04N1/50 ,  B41J2/315 ,  B41J2/32

    CPC分类号： H04N1/506

    摘要： Techniques are disclosed for performing color registration estimation and correction in a multi-head printer. A registration target is printed by the printer and captured by an image capture device (such as a camera) within the printer. The registration target includes a plurality of shapes, each of which is printed by a single one of the print heads in the printer, and which are arranged in a pattern designed to enable cross-web and down-web registration estimates to be generated. The printer analyzes the captured target to generate such cross-web and down-web registration estimates and thereby to generate cross-web and down-web registration corrections. The printer applies the registration corrections to subsequent print jobs, thereby reducing or eliminating misregistration in printed output. The techniques disclosed herein are suitable for use in printers having print heads that differ in resolution from each other.

    摘要翻译： 公开了用于在多头打印机中执行颜色注册估计和校正的技术。 注册目标由打印机打印并由打印机内的图像捕获设备（如照相机）捕获。 注册目标包括多个形状，每个形状由打印机中的单个打印头打印，并且以被设计成使得能够生成跨网页和下卷纸注册估计的图案布置。 打印机分析捕获的目标以产生这样的跨网络和下网络注册估计，从而产生跨网络和下网络注册校正。 打印机对后续打印作业进行注册修正，从而减少或消除打印输出中的对齐错误。 本文公开的技术适用于具有彼此分辨率不同的打印头的打印机。

    Multi-Chip-Module (MCM) microcircuit including multiple processors and Advanced Programmable Interrupt Controller (APIC)
    4.
    发明授权
    Multi-Chip-Module (MCM) microcircuit including multiple processors and Advanced Programmable Interrupt Controller (APIC) 失效
    包括多个处理器和高级可编程中断控制器（APIC）的多芯片模块（MCM）微电路

    公开(公告)号：US5678057A

    公开(公告)日：1997-10-14

    申请号：US485865

    申请日：1995-06-07

    申请人： Michael D. Rostoker ,  Sushant Verman ,  Richard Egan ,  Jerry Erh Hsiung Chow

    发明人： Michael D. Rostoker ,  Sushant Verman ,  Richard Egan ,  Jerry Erh Hsiung Chow

    IPC分类号： G06F13/24 ,  G06F13/14

    CPC分类号： G06F13/24

    摘要： A Multi-Chip-Module (MCM) microcircuit comprises a substrate, a plurality of integrated circuit processors mounted on the substrate, and an Advanced Programmable Interrupt Controller (APIC) system for distributing interrupts to the processors. The APIC system comprises a plurality of local units for prioritizing and passing interrupts to the processors respectively, and an Input/Output (I/O) unit for feeding interrupts to processors to which the interrupts are addressed. Electrical conductor patterns are formed on and between dielectric layers of the substrate for interconnecting the processors, the local units and the I/O unit.

    摘要翻译： 多芯片模块（MCM）微电路包括衬底，安装在衬底上的多个集成电路处理器，以及用于将中断分配给处理器的高级可编程中断控制器（APIC）系统。 APIC系统包括多个本地单元，用于分别对中断进行优先级排序和中断处理，以及一个输入/输出（I / O）单元，用于向中断寻址的处理器提供中断。 电导体图案形成在用于互连处理器，本地单元和I / O单元的基板的介电层之间和之间。

    Asynchronous transfer mode (ATM) interconnection system for multiple hosts including advanced programmable interrupt controller (APIC)
    6.
    发明授权
    Asynchronous transfer mode (ATM) interconnection system for multiple hosts including advanced programmable interrupt controller (APIC) 失效
    用于多个主机的异步传输模式（ATM）互连系统，包括高级可编程中断控制器（APIC）

    公开(公告)号：US5623494A

    公开(公告)日：1997-04-22

    申请号：US472475

    申请日：1995-06-07

    申请人： Michael D. Rostoker ,  Sushant Verman ,  Richard Egan ,  Jerry E. Chow

    发明人： Michael D. Rostoker ,  Sushant Verman ,  Richard Egan ,  Jerry E. Chow

    IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04U3/08

    CPC分类号： H04Q11/0478 ,  H04L2012/5615 ,  H04L2012/5616

    摘要： A system of the invention connects an Asynchronous Transfer Mode (ATM) data network to a plurality of host units. The data network transfers data in the form of ATM cells. A plurality of ATM termination units are connected between the network and the host units respectively. Each termination unit includes a virtual channel memory for storing ATM cells; a processor for segmenting and reassembling the ATM cells stored in the memory; a network interface for transferring ATM cells including segmented Conversion Sublayer Payload Data Units (CS-PDU)s between the memory, the processor and an ATM network; and a host interface for transferring unsegmented CS-PDUs between the memory, the processor and a host unit. The processor of each termination unit includes a computing unit, and a programmable instruction memory for storing a program for controlling the computing unit. The system further includes an Advanced Programmable Interrupt Controller (APIC) system for distributing interrupts from the network to the host units. The APIC system includes a plurality of local units for prioritizing and passing interrupts to the termination units respectively; and an Input/Output (I/O) unit for receiving interrupts from the network, determining to which host units interrupts are addressed, and feeding interrupts to local units corresponding to host units to which interrupts are addressed. Termination units and corresponding APIC local units may be formed on a single integrated circuit chip, and the chip may include ATM I/O units and/or processors constituting the host.

    摘要翻译： 本发明的系统将异步传输模式（ATM）数据网络连接到多个主机单元。 数据网络以ATM信元的形式传输数据。 多个ATM终端单元分别连接在网络和主机单元之间。 每个终端单元包括用于存储ATM信元的虚拟通道存储器; 用于分割和重组存储在存储器中的ATM信元的处理器; 用于在存储器，处理器和ATM网络之间传送包括分段转换子层有效载荷数据单元（CS-PDU）的ATM信元的网络接口; 以及用于在存储器，处理器和主机单元之间传送未分段的CS-PDU的主机接口。 每个终端单元的处理器包括计算单元和用于存储用于控制计算单元的程序的可编程指令存储器。 该系统还包括用于将中断从网络分发到主机单元的高级可编程中断控制器（APIC）系统。 APIC系统包括多个本地单元，用于分别优先排序并将中断传递给终端单元; 以及用于从网络接收中断的输入/输出（I / O）单元，确定哪个主机单元中断被寻址，以及将中断馈送给对应于中断被寻址的主机单元的本地单元。 终端单元和对应的APIC本地单元可以形成在单个集成电路芯片上，并且芯片可以包括构成主机的ATM I / O单元和/或处理器。

    Method of sampling bodily fluids
    8.
    发明授权
    Method of sampling bodily fluids 失效
    体液取样方法

    公开(公告)号：US06171868B2

    公开(公告)日：2001-01-09

    申请号：US08367508

    申请日：1994-12-30

    申请人： Noel Rolon ,  William Pagels ,  Richard Egan

    发明人： Noel Rolon ,  William Pagels ,  Richard Egan

    IPC分类号： G01N100

    CPC分类号： G01N1/286 ,  G01N1/08 ,  Y10T436/25

    摘要： The invention provides for a method of making more than one punchout from a single dried blood spot. The method comprising the steps of making a first punch and sequentially making at least a second punch in the dried blood spot. The second punch comprises boundaries which are at least partly outside of the boundaries of the first punch. The surface areas of the first punch and second punch are together equivalent to the minimum surface area required for testing of the dried blood spot.

    摘要翻译： 本发明提供了从单个干血点形成多于一种的方法。 该方法包括以下步骤：在干燥的血斑中制作第一冲头并依次制作至少第二冲头。 第二冲头包括至少部分在第一冲头的边界之外的边界。 第一冲头和第二冲头的表面积一起等于测试干血点所需的最小表面积。

    Advanced programmable interrupt controller (APIC) with high speed serial data bus
    9.
    发明授权
    Advanced programmable interrupt controller (APIC) with high speed serial data bus 失效
    高级可编程中断控制器（APIC），具有高速串行数据总线

    公开(公告)号：US5832279A

    公开(公告)日：1998-11-03

    申请号：US863373

    申请日：1997-05-27

    申请人： Michael D. Rostoker ,  Sushant Verman ,  Richard Egan ,  Jerry Chow

    发明人： Michael D. Rostoker ,  Sushant Verman ,  Richard Egan ,  Jerry Chow

    IPC分类号： G06F9/48 ,  G06F13/24 ,  G06F9/46

    CPC分类号： G06F9/4812 ,  G06F13/24 ,  Y02B60/1228 ,  Y02B60/144

    摘要： A high speed Advanced Programmable Interrupt Controller (APIC) system includes a plurality of local units for prioritizing and passing interrupts, an Input/Output (I/O) unit for feeding interrupts to the local units, and a serial link data transmission system for interconnecting the I/O unit and the local units. The I/O unit and each local unit have a parallel I/O interface. The serial link transmission system includes a parallel signal bus connected to the parallel I/O interface of the I/O unit; a plurality of first serial link transceivers having parallel I/O interfaces connected to the parallel signal bus, and serial I/O interfaces respectively; a plurality of second serial link transceivers having parallel I/O interfaces connected to the parallel I/O interfaces of the local units, and serial I/O interfaces respectively; and a plurality of serial transmission lines interconnecting the serial I/O interfaces of first serial link transceivers and the serial I/O interfaces of second serial link transceivers respectively.

    摘要翻译： 高速高级可编程中断控制器（APIC）系统包括用于对中断进行优先排序和通过的多个本地单元，用于向本地单元馈送中断的输入/输出（I / O）单元和用于互连的串行链路数据传输系统 I / O单元和本地单元。 I / O单元和本地单元具有并行I / O接口。 串行链路传输系统包括连接到I / O单元的并行I / O接口的并行信号总线; 具有分别连接到并行信号总线和串行I / O接口的并行I / O接口的多个第一串行链路收发器; 具有连接到本地单元的并行I / O接口的并行I / O接口的多个第二串行链路收发器和串行I / O接口; 以及分别将第一串行链路收发器的串行I / O接口和第二串行链路收发器的串行I / O接口互连的多个串行传输线。