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    Print Processing for Patterned Conductor, Semiconductor and Dielectric Materials
    2.
    发明申请
    Print Processing for Patterned Conductor, Semiconductor and Dielectric Materials 有权
    图案导体，半导体和电介质材料的印刷加工

    公开(公告)号：US20090065776A1

    公开(公告)日：2009-03-12

    申请号：US12114741

    申请日：2008-05-02

    申请人： Erik SCHER ,  Steven Molesa ,  Joerg Rockenberger ,  Arvind Kamath ,  Ikuo Mori

    发明人： Erik SCHER ,  Steven Molesa ,  Joerg Rockenberger ,  Arvind Kamath ,  Ikuo Mori

    IPC分类号： H01L29/04 ,  C08L83/00 ,  H01L29/06 ,  H01L29/16 ,  H01L21/208

    CPC分类号： C09D5/24 ,  C09D11/101 ,  C09D11/322 ,  C09D11/36 ,  C09D11/54 ,  H01B3/02 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28008 ,  H01L27/1292 ,  H01L29/6675 ,  H01L29/78696 ,  Y10T428/24802

    摘要： Embodiments relate to printing features from an ink containing a material precursor. In some embodiments, the material includes an electrically active material, such as a semiconductor, a metal, or a combination thereof. In another embodiment, the material includes a dielectric. The embodiments provide improved printing process conditions that allow for more precise control of the shape, profile and dimensions of a printed line or other feature. The composition(s) and/or method(s) improve control of pinning by increasing the viscosity and mass loading of components in the ink. An exemplary method thus includes printing an ink comprising a material precursor and a solvent in a pattern on the substrate; precipitating the precursor in the pattern to form a pinning line; substantially evaporating the solvent to form a feature of the material precursor defined by the pinning line; and converting the material precursor to the patterned material.

    摘要翻译： 实施例涉及从含有材​​料前体的油墨印刷特征。 在一些实施例中，材料包括电活性材料，例如半导体，金属或其组合。 在另一个实施例中，该材料包括电介质。 这些实施例提供改进的印刷工艺条件，其允许更精确地控制印刷线或其它特征的形状，轮廓和尺寸。 组合物和/或方法通过增加油墨中组分的粘度和质量负载来改善对钉扎的控制。 因此，示例性方法包括在基板上以图案印刷包含材料前体和溶剂的油墨; 以图案沉淀前体以形成钉扎线; 基本上蒸发溶剂以形成由钉扎线限定的材料前体的特征; 并将材料前体转化成图案化材料。

    Methods of making metal silicide contacts, interconnects, and/or seed layers
    4.
    发明授权
    Methods of making metal silicide contacts, interconnects, and/or seed layers 有权
    制造金属硅化物接触，互连和/或种子层的方法

    公开(公告)号：US08158518B2

    公开(公告)日：2012-04-17

    申请号：US12175450

    申请日：2008-07-17

    申请人： Aditi Chandra ,  Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Mao Takashima ,  Erik Scher

    发明人： Aditi Chandra ,  Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Mao Takashima ,  Erik Scher

    IPC分类号： H01L21/44

    CPC分类号： H01L21/288 ,  H01L21/28518 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76873 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L29/458 ,  H01L29/78618 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. The method of forming contacts includes depositing an ink of a silicide-forming metal onto an exposed silicon surface, drying the ink to form a silicide-forming metal precursor, and heating the silicide-forming metal precursor and the silicon surface to form a metal silicide contact. Optionally, the metal precursor ink may be selectively deposited onto a dielectric layer adjacent to the exposed silicon surface to form a metal-containing interconnect. Furthermore, one or more bulk conductive metal(s) may be deposited on remaining metal precursor ink and/or the dielectric layer. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching.

    摘要翻译： 公开了使用包含硅化物形成金属的油墨形成触点（和任选的局部互连）的方法，诸如二极管和/或包括这种触点的晶体管的电气器件，（可选的）局部互连）以及用于形成这种器件的方法。 形成接触的方法包括将硅化物形成金属的油墨沉积到暴露的硅表面上，干燥油墨以形成形成硅化物的金属前体，以及加热形成硅化物的金属前体和硅表面以形成金属硅化物 联系。 任选地，可以将金属前体油墨选择性地沉积到与暴露的硅表面相邻的电介质层上，以形成含金属互连。 此外，一个或多个体导电金属可以沉积在剩余的金属前体油墨和/或介电层上。 可以使用这种印刷的接触和/或局部互连来制造电子器件，例如二极管和晶体管。 金属墨水可以同时印刷以用于接触以及局部互连，或者替代地，如果需要用于接触和互连线的不同金属，印刷金属可以用作其它金属的无电沉积的种子 。 这种方法有利地减少了处理步骤的数量，并且不一定需要任何蚀刻。

    Profile engineered, electrically active thin film devices
    6.
    发明授权
    Profile engineered, electrically active thin film devices 有权
    型材设计，电活性薄膜器件

    公开(公告)号：US08426905B2

    公开(公告)日：2013-04-23

    申请号：US12243880

    申请日：2008-10-01

    申请人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    发明人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    IPC分类号： H01L29/788

    CPC分类号： H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

    摘要： The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

    摘要翻译： 本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法 通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。 平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。 本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。 这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。 均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

    Profile engineered thin film devices and structures
    7.
    发明授权
    Profile engineered thin film devices and structures 有权
    型材设计薄膜器件和结构

    公开(公告)号：US08822301B2

    公开(公告)日：2014-09-02

    申请号：US13791721

    申请日：2013-03-08

    申请人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    发明人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    IPC分类号： H01L21/20

    CPC分类号： H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

    摘要： The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

    摘要翻译： 本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法 通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。 平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。 本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。 这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。 均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

    Printed Dopant Layers
    8.
    发明申请
    Printed Dopant Layers 有权
    印刷掺杂层

    公开(公告)号：US20140094004A1

    公开(公告)日：2014-04-03

    申请号：US13633816

    申请日：2012-10-02

    申请人： Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zürcher

    发明人： Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zürcher

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1292 ,  H01L29/66757

    摘要： A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

    摘要翻译： 一种用于制造诸如MOS晶体管的电子器件的方法，包括以下步骤：在电功能衬底上形成多个半导体岛，在第一半导体岛子集上或第二子体上印刷第一介电层， 在半导体岛的第二子集上或之上，以及退火。 第一介电层包含第一掺杂剂，并且（任选的）第二介电层包含不同于第一掺杂剂的第二掺杂剂。 电介质层，半导体岛和衬底被充分退火以将第一掺杂剂扩散到半导体岛的第一子集中，并且当存在时将第二掺杂剂扩散到半导体岛的第二子集中。

    Printed dopant layers
    9.
    发明授权
    Printed dopant layers 有权
    印刷掺杂剂层

    公开(公告)号：US07701011B2

    公开(公告)日：2010-04-20

    申请号：US11888942

    申请日：2007-08-03

    申请人： Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zürcher

    发明人： Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zürcher

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L27/12 ,  H01L27/1292 ,  H01L29/78618

    摘要： An electronic device, including a substrate, a plurality of first semiconductor islands on the substrate, a plurality of second semiconductor islands on the substrate, a first dielectric film on the first subset of the semiconductor islands, second dielectric film on the second semiconductor islands, and a metal layer in electrical contact with the first and second semiconductor islands. The first semiconductor islands and the first dielectric film contain a first diffusible dopant, and the second semiconductor islands and the second dielectric layer film contain a second diffusible dopant different from the first diffusible dopant. The present electronic device can be manufactured using printing technologies, thereby enabling high-throughput, low-cost manufacturing of electrical circuits on a wide variety of substrates.

    摘要翻译： 一种电子器件，包括衬底，衬底上的多个第一半导体岛，衬底上的多个第二半导体岛，半导体岛的第一子集上的第一电介质膜，第二半导体岛上的第二电介质膜， 以及与第一和第二半导体岛电接触的金属层。 第一半导体岛和第一介电膜包含第一可扩散掺杂剂，第二半导体岛和第二介电层膜含有不同于第一可扩散掺杂剂的第二可扩散掺杂物。 本电子装置可以使用印刷技术制造，从而能够在各种基板上实现高通量，低成本的电路制造。

    PRINTED, SELF-ALIGNED, TOP GATE THIN FILM TRANSISTOR
    10.
    发明申请
    PRINTED, SELF-ALIGNED, TOP GATE THIN FILM TRANSISTOR 审中-公开
    打印，自对准，顶盖薄膜晶体管

    公开(公告)号：US20140299883A1

    公开(公告)日：2014-10-09

    申请号：US14311044

    申请日：2014-06-20

    申请人： Joerg ROCKENBERGER ,  James Montague Cleeves ,  Arvind Kamath

    发明人： Joerg ROCKENBERGER ,  James Montague Cleeves ,  Arvind Kamath

    IPC分类号： H01L29/786

    CPC分类号： H01L29/7866 ,  B82Y10/00 ,  H01L27/1248 ,  H01L27/1292 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78681 ,  H01L29/7869

    摘要： A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.

    摘要翻译： 一种自对准顶栅薄膜晶体管（TFT）和通过形成半导体薄膜层形成这种薄膜晶体管的方法; 在其上印刷掺杂的玻璃图案，所述掺杂玻璃图案中的间隙限定所述TFT的沟道区域; 在沟道区域上或上方形成栅电极，栅电极在其上包括栅介质膜和栅极导体; 并且将掺杂剂从掺杂的玻璃图案扩散到半导体薄膜层中。