公开(公告)号：US20100210509A1

公开(公告)日：2010-08-19

申请号：US12680955

申请日：2008-10-09

申请人： Eun-Ju Oh ,  Jung-Wook Kim ,  Sung-Ho Ryu ,  Sei-Kwang Hahn

发明人： Eun-Ju Oh ,  Jung-Wook Kim ,  Sung-Ho Ryu ,  Sei-Kwang Hahn

IPC分类号： A61K38/16 ,  C07K9/00

CPC分类号： C07K7/06 ,  A61K47/61

摘要： The invention relates to a novel bioconjugation protocol for peptide suitable for in vivo applications. Bioconjugation of the peptide to HA derivative increases its half life in circulation contributing for a high efficacy. More over, conjugate of HA derivative and peptide which is treated with hyaluronidase shows increased bioactivity. And also, in contrast to PEGylation, HA derivative can be conjugated with many numbers of peptide molecules per single HA derivative chain, which enables multiple action of peptide drugs.

摘要翻译： 本发明涉及适用于体内应用的肽的新型生物缀合方案。 肽与HA衍生物的生物共轭增加其循环的半衰期有助于高效力。 更具体地，HA衍生物和用透明质酸酶处理的肽的缀合物显示增加的生物活性。 而且，与聚乙二醇化相反，HA衍生物可以与单个HA衍生物链中的许多肽分子缀合，这使得肽药物能够多次作用。

公开(公告)号：US20060264025A1

公开(公告)日：2006-11-23

申请号：US11434146

申请日：2006-05-16

申请人： Jung-Wook Kim

发明人： Jung-Wook Kim

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/485 ,  H01L21/76846 ,  H01L21/76898 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a stacked semiconductor device and method of manufacturing the same, an insulation multilayer pattern is formed on a substrate. The insulation multilayer pattern includes a first insulating interlayer pattern, a second insulating interlayer pattern and an opening exposing a surface of the substrate. A first channel pattern may be interposed between the first insulating interlayer pattern and the second insulating interlayer pattern, with a sidewall of the channel pattern being exposed through the opening. A barrier metal layer including a first continuous sub-layer is provided along a sidewall and bottom surface of the opening. The first sub-layer may have a substantially uniform thickness around the first channel pattern.

摘要翻译： 在层叠半导体器件及其制造方法中，在基板上形成绝缘多层图案。 绝缘多层图案包括第一绝缘层间图案，第二绝缘层间图案和暴露基板表面的开口。 可以在第一绝缘层间图案和第二绝缘层间图案之间插入第一沟槽图案，通道图案的侧壁通过开口露出。 沿着开口的侧壁和底表面设置包括第一连续子层的阻挡金属层。 第一子层可以围绕第一通道图案具有基本均匀的厚度。

公开(公告)号：US07719045B2

公开(公告)日：2010-05-18

申请号：US12251352

申请日：2008-10-14

申请人： Young-Joo Cho ,  Hyun-Seok Lim ,  Rak-Hwan Kim ,  Jung-Wook Kim ,  Hyun-Suk Lee

发明人： Young-Joo Cho ,  Hyun-Seok Lim ,  Rak-Hwan Kim ,  Jung-Wook Kim ,  Hyun-Suk Lee

IPC分类号： H01L27/108

CPC分类号： H01L28/90 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/75

摘要： In a capacitor having a high dielectric constant, the capacitor includes a cylindrical lower electrode, a dielectric layer and an upper electrode. A metal oxide layer is formed on inner, top and outer surfaces of the lower electrode as the dielectric layer. A first sub-electrode is formed on a surface of the dielectric layer along the profile of the lower electrode and a second sub-electrode is continuously formed on the first sub-electrode corresponding to the top surface of the lower electrode, so an opening portion of the lower electrode is covered with the second sub-electrode. The first and second sub-electrodes include first and second metal nitride layers in which first and second stresses are applied, respectively. Directions of the first and second stresses are opposite to each other. Accordingly, cracking is minimized in the upper electrode with the high dielectric constant, thereby reducing current leakage.

摘要翻译： 在具有高介电常数的电容器中，电容器包括圆柱形下电极，电介质层和上电极。 在作为电介质层的下电极的内表面，顶面和外表面上形成金属氧化物层。 第一子电极沿着下电极的轮廓在电介质层的表面上形成，并且第二子电极连续形成在与下电极的顶表面对应的第一子电极上，因此开口部分 的下部电极被第二子电极覆盖。 第一和第二子电极分别包括施加第一和第二应力的第一和第二金属氮化物层。 第一和第二个应力的方向彼此相反。 因此，在具有高介电常数的上电极中破裂最小化，从而减少电流泄漏。

公开(公告)号：US07629262B2

公开(公告)日：2009-12-08

申请号：US11282193

申请日：2005-11-18

申请人： Jung-Wook Kim ,  Young-Joo Cho

发明人： Jung-Wook Kim ,  Young-Joo Cho

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface area results in an increased capacitance. An excessive etch phenomenon, which occurs because a sacrificial oxide layer is etched at a higher rate than the mold oxide layer, is avoided.

摘要翻译： 在一个实施例中，在半导体存储器件中形成电容器的下电极的方法包括将模具氧化物层蚀刻成具有圆柱形结构，导致具有增加的表面积的电极。 圆柱形结构可以具有多于一个的半径。 这种增加的表面积导致增加的电容。 避免了由于牺牲氧化物层以比模具氧化物层更高的速率蚀刻而发生的过度蚀刻现象。

公开(公告)号：US20060113580A1

公开(公告)日：2006-06-01

申请号：US11286316

申请日：2005-11-23

申请人： Young-Joo Cho ,  Hyun-Seok Lim ,  Rak-Hwan Kim ,  Jung-Wook Kim ,  Hyun-Suk Lee

发明人： Young-Joo Cho ,  Hyun-Seok Lim ,  Rak-Hwan Kim ,  Jung-Wook Kim ,  Hyun-Suk Lee

IPC分类号： H01L21/00

CPC分类号： H01L28/90 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/75

摘要： In a capacitor having a high dielectric constant, the capacitor includes a cylindrical lower electrode, a dielectric layer and an upper electrode. A metal oxide layer is formed on inner, top and outer surfaces of the lower electrode as the dielectric layer. A first sub-electrode is formed on a surface of the dielectric layer along the profile of the lower electrode and a second sub-electrode is continuously formed on the first sub-electrode corresponding to the top surface of the lower electrode, so an opening portion of the lower electrode is covered with the second sub-electrode. The first and second sub-electrodes include first and second metal nitride layers in which first and second stresses are applied, respectively. Directions of the first and second stresses are opposite to each other. Accordingly, cracking is minimized in the upper electrode with the high dielectric constant, thereby reducing current leakage.

摘要翻译： 在具有高介电常数的电容器中，电容器包括圆柱形下电极，电介质层和上电极。 在作为电介质层的下电极的内表面，顶面和外表面上形成金属氧化物层。 第一子电极沿着下电极的轮廓在电介质层的表面上形成，并且第二子电极连续形成在与下电极的顶表面对应的第一子电极上，因此开口部分 的下部电极被第二子电极覆盖。 第一和第二子电极分别包括施加第一和第二应力的第一和第二金属氮化物层。 第一和第二个应力的方向彼此相反。 因此，在具有高介电常数的上电极中破裂最小化，从而减少电流泄漏。

公开(公告)号：US20060115946A1

公开(公告)日：2006-06-01

申请号：US11282193

申请日：2005-11-18

申请人： Jung-Wook Kim ,  Young-Joo Cho

发明人： Jung-Wook Kim ,  Young-Joo Cho

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface area results in an increased capacitance. An excessive etch phenomenon, which occurs because a sacrificial oxide layer is etched at a higher rate than the mold oxide layer, is avoided.

公开(公告)号：US07037828B2

公开(公告)日：2006-05-02

申请号：US10916303

申请日：2004-08-10

申请人： Jung-Wook Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Jung-Wook Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： H01L21/44

CPC分类号： H01L23/485 ,  H01L21/76841 ,  H01L21/7685 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, and a method of fabricating the same, includes cobalt as a capping layer. An interconnection structure of the semiconductor device has an improved via resistance. In the semiconductor device, a single cobalt layer or a composite film including a cobalt layer and a titanium nitride layer is used as the capping layer of a metal layer.

摘要翻译： 半导体器件及其制造方法包括钴作为覆盖层。 半导体器件的互连结构具有改善的通孔电阻。 在半导体器件中，使用单个钴层或包含钴层和氮化钛层的复合膜作为金属层的覆盖层。

公开(公告)号：US20050046027A1

公开(公告)日：2005-03-03

申请号：US10916303

申请日：2004-08-10

申请人： Jung-Wook Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Jung-Wook Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L21/4763 ,  H01L29/40

CPC分类号： H01L23/485 ,  H01L21/76841 ,  H01L21/7685 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, and a method of fabricating the same, includes cobalt as a capping layer. An interconnection structure of the semiconductor device has an improved via resistance. In the semiconductor device, a single cobalt layer or a composite film including a cobalt layer and a titanium nitride layer is used as the capping layer of a metal layer.

摘要翻译： 半导体器件及其制造方法包括钴作为覆盖层。 半导体器件的互连结构具有改善的通孔电阻。 在半导体器件中，使用单个钴层或包含钴层和氮化钛层的复合膜作为金属层的覆盖层。

公开(公告)号：US07832825B2

公开(公告)日：2010-11-16

申请号：US11322563

申请日：2006-01-03

申请人： Jung-Wook Kim ,  Eul-hwan Lee

发明人： Jung-Wook Kim ,  Eul-hwan Lee

IPC分类号： B41J2/205

CPC分类号： B41J29/393

摘要： The nozzle error correction method is provided for adjusting information of an output image to correct an error nozzle. A position of an error nozzle firing an ink amount different from a reference value is detected from a plurality of nozzles. A determination is made from an input image as to whether a current pixel for output is an error pixel of the detected error nozzle. A channel value of the error nozzle is set to a certain value if the current pixel is the error pixel. However, if the current pixel is not the error pixel, a determination is made as to whether an error pixel exists in a certain area around the current pixel. A value of the current pixel is then adjusted based on error information. Image-processing is performed in order for the current pixel to be outputted, if the error pixel exists in the certain area. Accordingly, degradation of a print speed and a shortened life span of the head are prevented.

摘要翻译： 提供喷嘴误差校正方法，用于调整输出图像的信息以校正误差喷嘴。 从多个喷嘴检测出喷射与基准值不同的墨量的误差喷嘴的位置。 从输入图像中确定当前输出像素是否是检测到的误差喷嘴的误差像素。 如果当前像素是误差像素，则误差喷嘴的通道值被设置为一定值。 然而，如果当前像素不是误差像素，则确定在当前像素周围的特定区域中是否存在误差像素。 然后根据错误信息调整当前像素的值。 如果误差像素存在于特定区域，则执行图像处理以便输出当前像素。 因此，防止打印速度的劣化和头部的缩短的使用寿命。

公开(公告)号：US20100166328A1

公开(公告)日：2010-07-01

申请号：US12646508

申请日：2009-12-23

申请人： Jung-Wook Kim

发明人： Jung-Wook Kim

IPC分类号： G06K9/46 ,  G06K9/36

CPC分类号： H04N19/68 ,  H04N19/186 ,  H04N19/60 ,  H04N19/895

摘要： The image encoder includes a block arrangement unit configured to chromatically subsample an externally input image signal and to arrange the image signal in units of a plurality of blocks, a plurality of Discrete Cosine Transform (DCT) units configured to perform DCT with respect to the image signal divided into the plurality of blocks, a plurality of quantization units configured to quantize the outputs of the plurality of DCT units, a delta modulation unit configured to perform Differential Pulse Code Modulation (DPCM) with respect to the outputs of the plurality of quantization units, a plurality of Huffman encoding units configured to encode the outputs of the delta modulation units using a Huffman encoding method, and a code connection unit configured to reconstruct the signals output from the plurality of Huffman encoding units in constant bit units and to output a compressed image signal. Since the image is encoded in parallel, it is possible to increase encoding speed.

摘要翻译： 图像编码器包括块排列单元，其被配置为对外部输入的图像信号进行色度子采样并以多个块为单位布置图像信号;多个离散余弦变换（DCT）单元，被配置为相对于图像执行DCT 信号分成多个块，多个量化单元，被配置为量化多个DCT单元的输出;增量调制单元，被配置为针对多个量化单元的输出执行差分脉码调制（DPCM） 多个霍夫曼编码单元，被配置为使用霍夫曼编码方法对增量调制单元的输出进行编码;以及代码连接单元，被配置为以恒定位单位重构从多个霍夫曼编码单元输出的信号，并输出压缩 图像信号。 由于图像是并行编码的，所以可以提高编码速度。