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1.发明申请SYSTEMS AND METHODS FOR CONCURRENTLY TESTING MASTER AND SLAVE DEVICES IN A SYSTEM ON A CHIP 有权在芯片系统中同时测试主设备和从设备的系统和方法公开(公告)号：US20160238654A1
公开(公告)日：2016-08-18
申请号：US14623293
申请日：2015-02-16
IPC分类号： G01R31/3177 , G06F13/40
CPC分类号： G06F13/4068 , G01R31/31707 , G01R31/31727
摘要： An integrated circuit includes a substrate, a master system on the substrate, a slave system on the substrate that is coupled to communicate with the master system, a first clock signal coupled to the master system, and a second clock signal coupled to the slave system. The master system is configured to isolate the slave system from the master system while a first test of the master system is conducted in parallel with a second test of the slave system. The master system uses the first clock signal during the first test and the slave system uses the second clock signal during the second test.
摘要翻译： 集成电路包括衬底，衬底上的主系统，耦合到与主系统通信的衬底上的从系统，耦合到主系统的第一时钟信号以及耦合到从系统的第二时钟信号 。 主系统被配置为在主系统的第一测试与从系统的第二测试并行地进行时将从系统与主系统隔离。 主系统在第一次测试期间使用第一个时钟信号，而从系统在第二次测试期间使用第二个时钟信号。
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2.发明申请SYSTEMS AND METHODS TO DYNAMICALLY CALIBRATE AND ADJUST GAINS IN A DIRECT CONVERSION RECEIVER 有权在直接转换接收器中动态校准和调整增益的系统和方法公开(公告)号：US20160380788A1
公开(公告)日：2016-12-29
申请号：US14749884
申请日：2015-06-25
IPC分类号： H04L25/06
CPC分类号： H03G3/3078 , H03D3/008 , H03D3/009 , H03G3/3068 , H04B1/30 , H04L25/061 , H04L25/066
摘要： Method embodiments are provided herein for dynamically calibrating and adjusting a direct conversion receiver system. One embodiment includes applying one or more gain control signals to one or more gain elements of a receiver system, where the applying one or more gain control signals results in a gain change to the receiver system; in response to the gain change, determining whether the receiver system exhibits a DC (direct conversion) offset; and in response to a determination that the receiver system exhibits the DC offset, applying one or more DC offset correction control signals to one or more gain elements of the receiver system, where the one or more DC offset correction signals are configured to correct the DC offset.
摘要翻译： 本文提供了用于动态校准和调整直接转换接收器系统的方法实施例。 一个实施例包括将一个或多个增益控制信号应用于接收机系统的一个或多个增益元件，其中施加一个或多个增益控制信号导致对接收机系统的增益改变; 响应于增益变化，确定接收机系统是否呈现DC（直接转换）偏移; 并且响应于确定接收机系统呈现DC偏移，将一个或多个DC偏移校正控制信号施加到接收机系统的一个或多个增益元件，其中一个或多个DC偏移校正信号被配置为校正DC 抵消。
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3.发明申请公开(公告)号：US20170366296A1
公开(公告)日：2017-12-21
申请号：US15260926
申请日：2016-09-09
IPC分类号： H04L1/00 , H04L12/26 , H04B17/318 , H04W4/00 , H04W84/18
摘要： Methods and systems are disclosed to adjust communication links within wireless networks based upon composite link quality indicators (LQIs). Packet communications are received by a network node through a communication link from a separate network node within a wireless network. The network node can also be configured to transmit packet communications from the network node through the communication link to the separate network node. The network node generates composite LQI measurements for the received packet communications, and the composite LQI measurements are based upon signal strength measurements for the received packet communications and also based upon signal quality measurements for the received packet communications. The network node then adjusts the communication link based upon the composite LQI measurements.
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公开(公告)号：US20160191231A1
公开(公告)日：2016-06-30
申请号：US14582186
申请日：2014-12-24
CPC分类号： H04L7/033 , H04B1/40 , H04B3/46 , H04J3/1652
摘要： A phase lock loop monitor circuit is disclosed. The phase lock loop monitor circuit may include a coarse tuning circuit operable to generate a coarse tune failure indicator, a frequency target lock detector circuit operable to generate a frequency target failure indicator, a cycle slip monitor circuit operable to generate a cycle slip lock failure indicator, and an abort logic circuit communicatively coupled to the coarse tuning circuit, the frequency target lock detector circuit, and the cycle slip monitor circuit, the abort logic circuit operable to generate a radio operation abort indicator based at least on the coarse tune failure indicator, the frequency target failure indicator, or the cycle slip lock failure indicator.
摘要翻译： 公开了一种锁相环监视电路。 锁相环监视电路可以包括可以产生粗调失灵指示器的粗调谐电路，可操作以产生频率目标故障指示器的频率目标锁定检测器电路，可操作以产生循环滑移锁定失效指示器的循环滑移监视器电路 以及通信地耦合到粗调谐电路，频率目标锁定检测器电路和循环滑移监视器电路的中止逻辑电路，所述中止逻辑电路可操作以至少基于所述粗调失调指示器生成无线电操作中止指示符， 频率目标故障指示器或循环滑动锁定故障指示器。
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公开(公告)号：US20160381581A1
公开(公告)日：2016-12-29
申请号：US14835437
申请日：2015-08-25
CPC分类号： H04L5/0048 , H04L27/0014 , H04L27/22 , H04L2027/003 , H04L2027/0034 , H04L2027/0048 , H04L2027/0095 , H04W84/12
摘要： Methods and system for carrier frequency offset (CFO) estimation are described. The method includes determining correlation values between a plurality of samples from a received signal and a plurality of reference signals corresponding to a plurality of CFO candidates. A set of correlation values which exceeds a threshold is determined and a corresponding CFO candidate for each correlation value in the set is selected. A CFO estimate based on an interpolation of selected CFO candidates is then calculated.
摘要翻译： 描述载波频率偏移（CFO）估计的方法和系统。 该方法包括从接收到的信号和对应于多个CFO候选的多个参考信号确定多个样本之间的相关值。 确定超过阈值的一组相关值，并且选择该集合中的每个相关值的对应的CFO候选。 然后计算基于所选CFO候选的内插的CFO估计。
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公开(公告)号：US20160174094A1
公开(公告)日：2016-06-16
申请号：US14572295
申请日：2014-12-16
发明人： KHURRAM WAHEED , CHRIS N. STOLL , JAYSON D. VOGLER
摘要： An integrated circuit includes a receiver portion, a transmitter portion, and a modulated phase locked loop. The receiver portion is for receiving a radio frequency (RF) signal at a receiver input of the receiver portion. The transmitter portion is for transmitting an RF signal at a transmitter output of the transmitter portion. The modulated phase locked loop (PLL) is shared between the receiver portion and the transmitter portion. The transmitter output and receiver input are coupled together in a loopback configuration during a test mode. The transmitter portion and the receiver portion are enabled concurrently while a modulated PLL signal is provided to the receiver portion from the transmitter portion via the loopback configuration.
摘要翻译： 集成电路包括接收器部分，发射器部分和调制锁相环。 接收机部分用于在接收机部分的接收机输入处接收射频（RF）信号。 发射机部分用于在发射机部分的发射机输出处发送RF信号。 调制锁相环（PLL）在接收机部分和发射机部分之间共享。 发射机输出和接收机输入在测试模式下以环回配置耦合在一起。 发射机部分和接收机部分同时被使能，而调制的PLL信号经由环回配置从发射机部分提供给接收机部分。
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公开(公告)号：US20160248430A1
公开(公告)日：2016-08-25
申请号：US14631305
申请日：2015-02-25
发明人： KHURRAM WAHEED , KEVIN B. TRAYLOR
CPC分类号： H03L7/099 , H03B5/124 , H03B5/1265 , H03C3/00 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/0975 , H03L7/081 , H03L7/197 , H03M3/422 , H03M7/165
摘要： An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (VCO). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal for generating the fractional portion of the high port modulation signal.
摘要翻译： 集成电路包括双端口调制器和压控振荡器（VCO）。 双端口调制器具有用于接收发射机调制信号的第一输入端，用于提供高端口调制信号的分数部分的第一输出端，用于提供高端口调制信号的整数部分的第二输出端和用于 提供低端口调制信号。 VCO耦合到双端口调制器，并且具有用于接收高端口调制信号的小数部分的第一输入端，用于接收高端口调制信号的整数部分的第二输入端，用于接收调谐信号的第三输入端 在低端口调制信号上，以及第一输出端用于输出RF信号。 双端口调制器提供用于产生高端口调制信号的小数部分的带符号单位信号。
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公开(公告)号：US20160173048A1
公开(公告)日：2016-06-16
申请号：US14565745
申请日：2014-12-10
发明人： KHURRAM WAHEED
CPC分类号： H04B17/21 , H03G3/001 , H03G3/3078
摘要： A receiver system includes an automatic gain control (AGC) module configured to control a first gain control signal to a first gain element having variable gain control. The receiver system also includes a DC (direct current) offset correction block coupled to the AGC module, the DC offset correction block configured to trigger the AGC module to output a set of calibration gain control signals to the first gain element and capture a set of DC offset measurements of a first signal received at the DC offset correction block, where the first signal is passed by the first gain element. The DC offset correction block is further configured to estimate one or more DC offset components using the set of DC offset measurements, and calculate a first correction control signal corresponding to a first gain level of the first gain element using the one or more DC offset components.
摘要翻译： 接收机系统包括自动增益控制（AGC）模块，其被配置为将第一增益控制信号控制到具有可变增益控制的第一增益元件。 接收机系统还包括耦合到AGC模块的DC（直流）偏移校正块，DC偏移校正块被配置为触发AGC模块将一组校准增益控制信号输出到第一增益元件并捕获一组 在DC偏移校正块处接收的第一信号的DC偏移测量，其中第一信号被第一增益元件传递。 DC偏移校正块还被配置为使用DC偏移测量集来估计一个或多个DC偏移分量，并且使用一个或多个DC偏移分量来计算与第一增益元件的第一增益电平对应的第一校正控制信号 。
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