公开(公告)号：US20170132003A1

公开(公告)日：2017-05-11

申请号：US14937093

申请日：2015-11-10

Applicant: Futurewei Technologies, Inc.

Inventor： Tong Sun ,  Ying Xu ,  Weizhong Chen

IPC: G06F9/30 ,  G06F9/48

CPC classification number: G06F9/3851 ,  G06F9/3853 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5027 ,  G06F2209/507 ,  Y02D10/22

Abstract: A system and method of hardware multithreading in VLIW DSPs includes an instruction fetch and dispatch unit, a plurality of program control units coupled to the instruction fetch and dispatch unit, a plurality of function units coupled to the plurality of program control units, and a mode control unit coupled to the function units and the program control units, the mode control unit configured to dynamically organize the plurality of function units and the plurality of program control units into one or more threads, each thread comprising a program control of the plurality of program control units and a subset of the plurality of function units.

公开(公告)号：US20180337808A1

公开(公告)日：2018-11-22

申请号：US15597357

申请日：2017-05-17

Applicant: Futurewei Technologies, Inc.

Inventor： Weizhong Chen ,  Tao Zhang

IPC: H04L27/26 ,  H04B7/04 ,  H04L25/02

CPC classification number: H04L27/265 ,  H04B7/04 ,  H04L25/0232 ,  H04L27/2628

Abstract: A segment-based approach for fast fourier transforms of input signals is provided for the generation of baseband signals. A FFT is performed individually for each of the segments from the input signal and the FFT result from each segment is accumulated to provide a final FFT for an input signal symbol. After the samples are received for one segment, a FFT can be performed to generate an intermediate FFT result while samples for the additional segment(s) are received. The system accumulates the intermediate result from the segments into a final FFT result that can be used to generate the baseband signal. Segment-based processing of an input signal can provide faster and more efficient processing to generate a baseband signal. Segment-based processing can also decrease the required size of the input buffers for antennas.

公开(公告)号：US20140161210A1

公开(公告)日：2014-06-12

申请号：US13711325

申请日：2012-12-11

Applicant: FUTUREWEI TECHNOLOGIES, INC.

Inventor： Weizhong Chen ,  Yuanbin Guo ,  Tong Sun

IPC: H04L27/00

CPC classification number: H04L27/00 ,  H04B1/0028 ,  H04B7/0854 ,  H04L25/03019 ,  H04L27/0008

Abstract: According to one embodiment, an apparatus includes a digital signal processor configured to perform a multiple antenna detection portion of a baseband signal processing process using a first floating point processing unit, and perform all other portions of the baseband signal processing process using a half-precision floating point processing unit. The first floating point processing unit has a bit width that is larger than the bit width of the half-precision floating point processing unit.

Abstract translation: 根据一个实施例，一种装置包括数字信号处理器，被配置为使用第一浮点处理单元执行基带信号处理处理的多天线检测部分，并且使用半精度执行基带信号处理处理的所有其它部分 浮点处理单元。 第一浮点处理单元具有比半精度浮点处理单元的位宽大的位宽度。

公开(公告)号：US20180217838A1

公开(公告)日：2018-08-02

申请号：US15422014

申请日：2017-02-01

Applicant: Futurewei Technologies, Inc.

Inventor： Weizhong Chen ,  Tong Sun ,  Bin Yang

IPC: G06F9/30 ,  H04W88/10 ,  G06F12/0875

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3012 ,  G06F9/3016 ,  G06F9/3885 ,  G06F12/0875 ,  G06F2212/452 ,  H04W88/10

Abstract: An apparatus comprises a central processor that outputs a first control signal to data organizers that organizes and moves data and a second control signal to vector processors that receives a first and second set of data from the data organizers. A first vector processor includes a first instruction circuit that executes a first plurality of vector functions and a second instruction circuit that executes a second plurality of vector functions. A first vector function is selected from the first plurality of vector functions to process the first set of data in response to the second control signal. Similarly, a second vector function is selected from the second plurality of vector functions to process the second set of data in response to the second control signal.

公开(公告)号：US09841999B2

公开(公告)日：2017-12-12

申请号：US14815871

申请日：2015-07-31

Applicant: Futurewei Technologies, Inc.

Inventor： Weizhong Chen ,  Bin Yang ,  Tong Sun

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/5016 ,  G06F9/5027 ,  G06F9/5094 ,  Y02D10/22

Abstract: An apparatus and method are provided for allocating resources to a plurality of threads to perform a service. In use, a request for service is received. At least one of a plurality of resources is allocated to the threads. Further, the service is performed with the threads, utilizing the allocated at least one resource.

公开(公告)号：US20170141938A1

公开(公告)日：2017-05-18

申请号：US14939185

申请日：2015-11-12

Applicant: Futurewei Technologies, Inc.

Inventor： Weizhong Chen ,  Junhong Nie

IPC: H04L25/03 ,  H04B1/40 ,  H04L5/14

CPC classification number: H04L25/03821 ,  H04B1/12 ,  H04B1/40 ,  H04B1/525 ,  H04L5/14

Abstract: A full-duplex transceiver with passive inter-modulation (PIM) cancellation using a feedforward filtering structure is presented. The transceiver can comprise a duplexer, a transmitter, a receiver, a summer, and a behavioral model module (BMM) that is used to estimate an estimated inter-modulated signal using a feedforward structure. The summer receives a receive signal output from the receiver and a compensation signal, and output a PIM compensated receive signal based on the difference between the receive signal output and the compensation signal. Further, the BMM receives the multiband transmit signal input and the PIM compensated receive signal, where the BMM tunes the transceiver to output a PIM compensated receive signal. The BMM generates an estimated compensation signal from an align term, lag terms, and lead terms of the transmitted signals. The embodiments disclosed herein can be applicable to communication networks experiencing PIM distortion in a radio frequency chain.

公开(公告)号：US20170031717A1

公开(公告)日：2017-02-02

申请号：US14815871

申请日：2015-07-31

Applicant: Futurewei Technologies, Inc.

Inventor： Weizhong Chen ,  Bin Yang ,  Tong Sun

IPC: G06F9/50

CPC classification number: G06F9/5016 ,  G06F9/5027 ,  G06F9/5094 ,  Y02D10/22

Abstract: An apparatus and method are provided for allocating resources to a plurality of threads to perform a service. In use, a request for service is received. At least one of a plurality of resources is allocated to the threads. Further, the service is performed with the threads, utilizing the allocated at least one resource.

Abstract translation: 提供了一种用于向多个线程分配资源以执行服务的装置和方法。 在使用中，接收到服务请求。 多个资源中的至少一个被分配给线程。 此外，利用所分配的至少一个资源，利用线程执行服务。

公开(公告)号：US20180046435A1

公开(公告)日：2018-02-15

申请号：US15723924

申请日：2017-10-03

Applicant: Futurewei Technologies, Inc.

Inventor： Yuanbin Guo ,  Tong Sun ,  Weizhong Chen

IPC: G06F7/483

CPC classification number: G06F7/483

Abstract: An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.

公开(公告)号：US20170141807A1

公开(公告)日：2017-05-18

申请号：US14939183

申请日：2015-11-12

Applicant: Futurewei Technologies, Inc.

Inventor： Weizhong Chen ,  Junhong Nie

IPC: H04B1/40 ,  H04L5/14 ,  H04B1/525 ,  H04B1/12 ,  H04B1/10

Abstract: A full-duplex transceiver with passive inter-modulation (PIM) cancellation using feedforward plus a feedback filtering structure is presented. The transceiver comprises a duplexer, a transmitter, a receiver, a summer, and a behavioral model module (BMM) that is used to generate an estimated inter-modulated signal using a feedforward plus feedback structure. The summer receives a receive signal output from the receiver and an estimated compensation signal, and outputs a PIM compensated receive signal based on the difference between the receive signal output and the estimated compensation signal. Further, the BMM receives the multiband transmit signal input and the PIM compensated receive signal, and tunes the transceiver to output the PIM compensated receive signal. The BMM generates the estimated compensation signal from an align term, lag terms, lead terms, and feedback of the transmitted signals. The embodiments disclosed herein can be applicable to communication networks experiencing PIM distortion in a radio frequency chain.

公开(公告)号：US08971451B2

公开(公告)日：2015-03-03

申请号：US13711325

申请日：2012-12-11

Applicant: Futurewei Technologies, Inc.

Inventor： Weizhong Chen ,  Yuanbin Guo ,  Tong Sun

IPC: H04L27/00

CPC classification number: H04L27/00 ,  H04B1/0028 ,  H04B7/0854 ,  H04L25/03019 ,  H04L27/0008

Abstract: According to one embodiment, an apparatus includes a digital signal processor configured to perform a multiple antenna detection portion of a baseband signal processing process using a first floating point processing unit, and perform all other portions of the baseband signal processing process using a half-precision floating point processing unit. The first floating point processing unit has a bit width that is larger than the bit width of the half-precision floating point processing unit.

Abstract translation: 根据一个实施例，一种装置包括数字信号处理器，被配置为使用第一浮点处理单元执行基带信号处理处理的多天线检测部分，并且使用半精度执行基带信号处理处理的所有其它部分 浮点处理单元。 第一浮点处理单元具有比半精度浮点处理单元的位宽大的位宽度。