公开(公告)号：US20170017412A1

公开(公告)日：2017-01-19

申请号：US14797620

申请日：2015-07-13

Applicant: Futurewei Technologies, Inc.

Inventor： Hao Luan ,  Alan Gatherer ,  Bin Yang

IPC: G06F3/06

CPC classification number: G06F9/52 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0815 ,  G06F13/1663

Abstract: A controller for a shared memory is disclosed. The controller comprises a transaction scanner configured to scan-in a plurality of transactions to access the shared memory and to divide the transactions into beat-level memory access commands. The controller also comprises a command super-arbiter comprising a plurality of command arbiters corresponding to a plurality of shared memory blocks in the shared memory. The command super-arbiter is configured to access a quality of service for each of the transactions, arbitrate the beat-level memory access commands associated with the transactions based on the quality of service for each of the plurality of transactions, and dispatch the beat-level memory access commands to the shared memory blocks based on results of arbitrating the beat-level memory access commands.

Abstract translation: 公开了一种用于共享存储器的控制器。 控制器包括交易扫描器，其被配置为扫描多个事务以访问共享存储器并且将事务划分为节​​拍级存储器访问命令。 该控制器还包括一个命令超级仲裁器，其包括与共享存储器中的多个共享存储器块相对应的多个命令仲裁器。 命令超级仲裁器被配置为访问每个事务的服务质量，基于用于多个事务中的每一个的服务质量来仲裁与事务相关联的节拍级存储器访问命令， 基于对节拍级别存储器访问命令进行仲裁的结果，对共享存储器块的级别存储器访问命令。

公开(公告)号：US20180285290A1

公开(公告)日：2018-10-04

申请号：US15942065

申请日：2018-03-30

Applicant: Futurewei Technologies, Inc.

Inventor： Hao Luan ,  Alan Gatherer ,  Xi Chen ,  Fang Yu ,  Yichuan Yu ,  Bin Yang ,  Wei Chen

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A distributed and shared memory controller (DSMC) comprises at least one building block. comprising a plurality of switches distributed into a plurality of stages; a plurality of master ports coupled to a first stage of the switches; and a plurality of bank controllers with associated memory banks coupled to a last stage of the switches; wherein each of the switches connects to lower stage switches via internal connections, each of the switches of the first stage connects to at least one of the master ports via master connections and each of the switches of the last stage connects to at least one of the bank controllers via memory connections; wherein each of the switches of the first stage connects to second stage switches of a neighboring building block via outward connections and each of the switches of a second stage connects to first stage switches of the neighboring building block via inward connections.

公开(公告)号：US10769080B2

公开(公告)日：2020-09-08

申请号：US15942065

申请日：2018-03-30

Applicant: Futurewei Technologies, Inc.

Inventor： Hao Luan ,  Alan Gatherer ,  Xi Chen ,  Fang Yu ,  Yichuan Yu ,  Bin Yang ,  Wei Chen

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A distributed and shared memory controller (DSMC) comprises at least one building block. comprising a plurality of switches distributed into a plurality of stages; a plurality of master ports coupled to a first stage of the switches; and a plurality of bank controllers with associated memory banks coupled to a last stage of the switches; wherein each of the switches connects to lower stage switches via internal connections, each of the switches of the first stage connects to at least one of the master ports via master connections and each of the switches of the last stage connects to at least one of the bank controllers via memory connections; wherein each of the switches of the first stage connects to second stage switches of a neighboring building block via outward connections and each of the switches of a second stage connects to first stage switches of the neighboring building block via inward connections.

公开(公告)号：US10353747B2

公开(公告)日：2019-07-16

申请号：US14797620

申请日：2015-07-13

Applicant: Futurewei Technologies, Inc.

Inventor： Hao Luan ,  Alan Gatherer ,  Bin Yang

IPC: G06F12/00 ,  G06F9/52 ,  G06F3/06 ,  G06F13/16 ,  G06F12/0815

Abstract: A controller for a shared memory is disclosed. The controller comprises a transaction scanner configured to scan-in a plurality of transactions to access the shared memory and to divide the transactions into beat-level memory access commands. The controller also comprises a command super-arbiter comprising a plurality of command arbiters corresponding to a plurality of shared memory blocks in the shared memory. The command super-arbiter is configured to access a quality of service for each of the transactions, arbitrate the beat-level memory access commands associated with the transactions based on the quality of service for each of the plurality of transactions, and dispatch the beat-level memory access commands to the shared memory blocks based on results of arbitrating the beat-level memory access commands.

公开(公告)号：US20180217838A1

公开(公告)日：2018-08-02

申请号：US15422014

申请日：2017-02-01

Applicant: Futurewei Technologies, Inc.

Inventor： Weizhong Chen ,  Tong Sun ,  Bin Yang

IPC: G06F9/30 ,  H04W88/10 ,  G06F12/0875

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3012 ,  G06F9/3016 ,  G06F9/3885 ,  G06F12/0875 ,  G06F2212/452 ,  H04W88/10

Abstract: An apparatus comprises a central processor that outputs a first control signal to data organizers that organizes and moves data and a second control signal to vector processors that receives a first and second set of data from the data organizers. A first vector processor includes a first instruction circuit that executes a first plurality of vector functions and a second instruction circuit that executes a second plurality of vector functions. A first vector function is selected from the first plurality of vector functions to process the first set of data in response to the second control signal. Similarly, a second vector function is selected from the second plurality of vector functions to process the second set of data in response to the second control signal.

公开(公告)号：US09841999B2

公开(公告)日：2017-12-12

申请号：US14815871

申请日：2015-07-31

Applicant: Futurewei Technologies, Inc.

Inventor： Weizhong Chen ,  Bin Yang ,  Tong Sun

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/5016 ,  G06F9/5027 ,  G06F9/5094 ,  Y02D10/22

Abstract: An apparatus and method are provided for allocating resources to a plurality of threads to perform a service. In use, a request for service is received. At least one of a plurality of resources is allocated to the threads. Further, the service is performed with the threads, utilizing the allocated at least one resource.

公开(公告)号：US20170031717A1

公开(公告)日：2017-02-02

申请号：US14815871

申请日：2015-07-31

Applicant: Futurewei Technologies, Inc.

Inventor： Weizhong Chen ,  Bin Yang ,  Tong Sun

IPC: G06F9/50

CPC classification number: G06F9/5016 ,  G06F9/5027 ,  G06F9/5094 ,  Y02D10/22

Abstract: An apparatus and method are provided for allocating resources to a plurality of threads to perform a service. In use, a request for service is received. At least one of a plurality of resources is allocated to the threads. Further, the service is performed with the threads, utilizing the allocated at least one resource.

Abstract translation: 提供了一种用于向多个线程分配资源以执行服务的装置和方法。 在使用中，接收到服务请求。 多个资源中的至少一个被分配给线程。 此外，利用所分配的至少一个资源，利用线程执行服务。

公开(公告)号：US10296398B2

公开(公告)日：2019-05-21

申请号：US14797620

申请日：2015-07-13

Applicant: Futurewei Technologies, Inc.

Inventor： Hao Luan ,  Alan Gatherer ,  Bin Yang

IPC: G06F12/00 ,  G06F9/52 ,  G06F3/06 ,  G06F13/16 ,  G06F12/0815

Abstract: A controller for a shared memory is disclosed. The controller comprises a transaction scanner configured to scan-in a plurality of transactions to access the shared memory and to divide the transactions into beat-level memory access commands. The controller also comprises a command super-arbiter comprising a plurality of command arbiters corresponding to a plurality of shared memory blocks in the shared memory. The command super-arbiter is configured to access a quality of service for each of the transactions, arbitrate the beat-level memory access commands associated with the transactions based on the quality of service for each of the plurality of transactions, and dispatch the beat-level memory access commands to the shared memory blocks based on results of arbitrating the beat-level memory access commands.