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    Charge-pump device with increased current output
    5.
    发明授权
    Charge-pump device with increased current output 有权
    电荷泵装置，电流输出增加

    公开(公告)号：US07532060B2

    公开(公告)日：2009-05-12

    申请号：US11270308

    申请日：2005-11-09

    申请人： Carmela Albano ,  Daniele Vimercati

    发明人： Carmela Albano ,  Daniele Vimercati

    IPC分类号： G05F1/10

    CPC分类号： G11C16/30 ,  H02M3/073

    摘要： In a charge-pump device, a charge-pump circuit has an input, which is connected to a supply line and receives a supply voltage, and an output; in the charge-pump circuit a first elementary stage defines a first transfer node and a second transfer node that can be connected respectively to the input and to the output, and has at least one first phase input. In addition, in the first elementary stage a first switching element is arranged between the first transfer node and the second transfer node, has a control terminal receiving a control signal, and is closed during a charge-transfer interval; and first charge-storage means are connected between the control terminal and the first phase input. In the first elementary stage, a voltage-booster stage has an input connected to the first phase input of the first elementary stage, and an output connected to the first charge-storage means and supplies a boosted phase signal; in particular, the voltage-booster stage is operative during the charge-transfer interval.

    摘要翻译： 在电荷泵装置中，电荷泵电路具有连接到电源线并接收电源电压的输入和输出; 在电荷泵电路中，第一基本级定义可以分别连接到输入端和输出端的第一传输节点和第二传输节点，并具有至少一个第一相位输入。 另外，在第一基本阶段，第一开关元件被布置在第一转移节点和第二转移节点之间，控制终端接收控制信号，并且在电荷转移间隔期间闭合; 并且第一电荷存储装置连接在控制端和第一相输入之间。 在第一基本级中，升压级具有连接到第一基本级的第一相输入端的输入端和连接到第一电荷存储单元的输出端，并提供升压相位信号; 特别地，电压 - 升压级在电荷转移间隔期间是可操作的。

    Memory device with time-shifting based emulation of reference cells
    6.
    发明授权
    Memory device with time-shifting based emulation of reference cells 有权
    具有基于时移的参考单元仿真的存储器件

    公开(公告)号：US07345905B2

    公开(公告)日：2008-03-18

    申请号：US11367707

    申请日：2006-03-02

    申请人： Federico Pio ,  Efrem Bolandrina ,  Daniele Vimercati

    发明人： Federico Pio ,  Efrem Bolandrina ,  Daniele Vimercati

    IPC分类号： G11C17/00

    CPC分类号： G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

    摘要： A memory device includes a plurality of memory cells and a comparison circuit that compares a set of selected memory cells with at least one reference cell having a threshold voltage. The comparison circuit includes a bias circuit that applies a biasing voltage having a substantially monotone time pattern to the selected memory cells and to the at least one reference cell, sense amplifiers that detect the reaching of a comparison current by a cell current of each selected memory cell and by a reference current of each reference cell, a logic unit that determines a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and by the at least one reference current, and a time shift structure that time shifts at least one of said detections according to at least one predefined interval to emulate the comparison with at least one further reference cell having a further threshold voltage.

    摘要翻译： 存储器件包括多个存储器单元和比较电路，其将所选择的存储器单元组与至少一个具有阈值电压的参考单元进行比较。 比较电路包括偏置电路，该偏置电路将具有基本上单调的时间图案的偏置电压施加到所选择的存储器单元和至少一个参考单元，检测放大器，其通过每个选择的存储器的单元电流检测比较电流的到达 单元和每个参考单元的参考电流;逻辑单元，其根据比较电流到达相应的单元电流和至少一个参考电流的时间关系来确定每个选择的存储单元的状态;以及 时移结构，其根据至少一个预定间隔时间移动至少一个所述检测，以模拟与具有另一阈值电压的至少一个另外的参考小区的比较。

    Memory device with a ramp-like voltage biasing structure and reduced number of reference cells
    7.
    发明申请
    Memory device with a ramp-like voltage biasing structure and reduced number of reference cells 有权

    公开(公告)号：US20060215463A1

    公开(公告)日：2006-09-28

    申请号：US11368363

    申请日：2006-03-03

    申请人： Daniele Vimercati ,  Efrem Bolandrina

    发明人： Daniele Vimercati ,  Efrem Bolandrina

    IPC分类号： G11C7/06

    CPC分类号： G11C11/5642 ,  G11C16/32 ,  G11C2211/5634 ,  G11C2211/5645

    摘要： A memory device is proposed. The memory device includes a plurality of memory cells, means for comparing a set of selected memory cells with at least one reference cell having a predefined threshold voltage, the means for comparing including biasing means for applying a biasing voltage having a substantially monotonic time pattern to the selected memory cells and the at least one reference cell, means for detecting the reaching of a comparison current by a measure cell current corresponding to each selected memory cell and by a measure reference current corresponding to each reference cell, and means for determining a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding measure cell current and by the at least one measure reference current, wherein the means for comparing further includes means for selectively modifying at least one of said currents to emulate the comparison with at least one further reference cell having a further threshold voltage.

    Method for reading a nonvolatile memory device and nonvolatile memory device implementing the reading method
    8.
    发明授权
    Method for reading a nonvolatile memory device and nonvolatile memory device implementing the reading method 有权
    读取非易失性存储器件的方法和实现读取方法的非易失性存储器件

    公开(公告)号：US07054197B2

    公开(公告)日：2006-05-30

    申请号：US10820458

    申请日：2004-04-08

    申请人： Daniele Vimercati

    发明人： Daniele Vimercati

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

    摘要： A reading method for a nonvolatile memory device, wherein the gate terminals of the array memory cell and of the reference memory cell are supplied with a same reading voltage having a ramp-like pattern, so as to modify their current-conduction states in successive times, and the contents of the array memory cell are determined on the basis of the modification order of the current-conduction states of the array memory cell and of the reference memory cell.

    摘要翻译： 一种用于非易失性存储器件的读取方法，其中阵列存储单元和参考存储单元的栅极端子被提供有具有斜坡图案的相同读取电压，以便连续地修改其电流传导状态 并且基于阵列存储单元和参考存储单元的当前导通状态的修改顺序来确定阵列存储单元的内容。

    Method for generating a reference current for sense amplifiers and corresponding generator
    9.
    发明授权
    Method for generating a reference current for sense amplifiers and corresponding generator 失效
    用于产生读出放大器和相应发生器的参考电流的方法

    公开(公告)号：US07006025B2

    公开(公告)日：2006-02-28

    申请号：US10861340

    申请日：2004-06-04

    申请人： Stefan Schippers ,  Daniele Vimercati ,  Efrem Bolandrina

    发明人： Stefan Schippers ,  Daniele Vimercati ,  Efrem Bolandrina

    IPC分类号： H03M1/66 ,  G11C11/00

    CPC分类号： G11C16/28 ,  G11C7/14

    摘要： A method is described for generating a reference current for sense amplifiers connected to cells of a memory matrix comprising the steps of generating a first reference current analog signal through a reference cell, performing an analog-to-digital conversion of the first analog signal into a reference current digital signal, sending the digital signal on a connection line to the sense amplifiers, and performing a digital-to-analog conversion of the digital signal into a second reference current analog signal to be applied as reference current to the sense amplifiers.

    摘要翻译： 描述了一种用于产生连接到存储器矩阵的单元的读出放大器的参考电流的方法，包括以下步骤：通过参考单元产生第一参考电流模拟信号，执行第一模拟信号的模数转换为 参考电流数字信号，将连接线上的数字信号发送到感测放大器，并且将数字信号进行数模转换成第二参考电流模拟信号，以作为参考电流施加到感测放大器。

    Controlling clock input buffers
    10.
    发明授权
    Controlling clock input buffers 有权
    控制时钟输入缓冲区

    公开(公告)号：US08824235B2

    公开(公告)日：2014-09-02

    申请号：US13519846

    申请日：2009-12-30

    申请人： Daniele Balluchi ,  Daniele Vimercati ,  Graziano Mirichigni

    发明人： Daniele Balluchi ,  Daniele Vimercati ,  Graziano Mirichigni

    IPC分类号： G11C5/14

    CPC分类号： H03K3/012 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4072

    摘要： An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles of the clock signal, the buffer is automatically powered up.

    摘要翻译： 集成电路可以具有耦合到缓冲器（24）的时钟输入引脚。 缓冲器可以向诸如存储器的集成电路芯片提供时钟信号（28）。 为了节省电力，缓冲区掉电。 当准备使用时，缓冲区被快速备份。 在一个实施例中，响应于预定数量的时钟信号的切换，缓冲器自动上电。