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    Fabricating bipolar junction select transistors for semiconductor memories
    4.
    发明授权
    Fabricating bipolar junction select transistors for semiconductor memories 有权
    制造用于半导体存储器的双极结选择晶体管

    公开(公告)号：US08076211B2

    公开(公告)日：2011-12-13

    申请号：US12912829

    申请日：2010-10-27

    申请人： Agostino Pirovano ,  Augusto Benvenuti ,  Fabio Pellizzer ,  Giorgio Servalli

    发明人： Agostino Pirovano ,  Augusto Benvenuti ,  Fabio Pellizzer ,  Giorgio Servalli

    IPC分类号： H01L21/8222 ,  H01L21/331

    CPC分类号： H01L29/73 ,  H01L27/24

    摘要： A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced.

    摘要翻译： 双极结型晶体管可以用作半导体存储器的选择器件。 双极结晶体管可以由基极和集电极层的堆叠形成。 一组平行的沟槽沿着第一方向下降到底部并且沿着第二方向形成在收集器的下方。 沟槽可以用于在每个沟槽中的基底和收集器的暴露部分中形成局部增强植入物。 作为局部增强植入物的结果，在一些实施例中，泄漏电流可能降低，有效电流能力可能更高，增益可能更高，基极电阻可能降低，击穿电压可能增加，并且具有相邻接点的寄生效应 减少

    Fabricating bipolar junction select transistors for semiconductor memories
    5.
    发明授权
    Fabricating bipolar junction select transistors for semiconductor memories 有权
    制造用于半导体存储器的双极结选择晶体管

    公开(公告)号：US07847373B2

    公开(公告)日：2010-12-07

    申请号：US12341027

    申请日：2008-12-22

    申请人： Agostino Pirovano ,  Augusto Benvenuti ,  Fabio Pellizzer ,  Giorgio Servalli

    发明人： Agostino Pirovano ,  Augusto Benvenuti ,  Fabio Pellizzer ,  Giorgio Servalli

    IPC分类号： H01L27/082 ,  H01L27/102 ,  H01L29/70

    CPC分类号： H01L29/73 ,  H01L27/24

    摘要： A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced.

    摘要翻译： 双极结型晶体管可以用作半导体存储器的选择器件。 双极结晶体管可以由基极和集电极层的堆叠形成。 一组平行的沟槽沿着第一方向下降到底部并且沿着第二方向形成在收集器的下方。 沟槽可以用于在每个沟槽中的基底和收集器的暴露部分中形成局部增强植入物。 作为局部增强植入物的结果，在一些实施例中，泄漏电流可能降低，有效电流能力可能更高，增益可能更高，基极电阻可能降低，击穿电压可能增加，并且具有相邻接点的寄生效应 减少

    Fabricating Bipolar Junction Select Transistors for Semiconductor Memories
    6.
    发明申请
    Fabricating Bipolar Junction Select Transistors for Semiconductor Memories 有权
    制造半导体存储器的双极结选择晶体管

    公开(公告)号：US20110039391A1

    公开(公告)日：2011-02-17

    申请号：US12912829

    申请日：2010-10-27

    申请人： Agostino Pirovano ,  Augusto Benvenuti ,  Fabio Pellizzer ,  Giorgio Servalli

    发明人： Agostino Pirovano ,  Augusto Benvenuti ,  Fabio Pellizzer ,  Giorgio Servalli

    IPC分类号： H01L21/331

    CPC分类号： H01L29/73 ,  H01L27/24

    摘要： A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced.

    摘要翻译： 双极结型晶体管可以用作半导体存储器的选择器件。 双极结晶体管可以由基极和集电极层的堆叠形成。 一组平行的沟槽沿着第一方向下降到底部并且沿着第二方向形成在收集器的下方。 沟槽可以用于在每个沟槽中的基底和收集器的暴露部分中形成局部增强植入物。 作为局部增强植入物的结果，在一些实施例中，泄漏电流可能降低，有效电流能力可能更高，增益可能更高，基极电阻可能降低，击穿电压可能增加，并且具有相邻接点的寄生效应 减少

    PROCESS FOR MANUFACTURING AN ARRAY OF CELLS INCLUDING SELECTION BIPOLAR JUNCTION TRANSISTORS WITH PROJECTING CONDUCTION REGIONS
    7.
    发明申请
    PROCESS FOR MANUFACTURING AN ARRAY OF CELLS INCLUDING SELECTION BIPOLAR JUNCTION TRANSISTORS WITH PROJECTING CONDUCTION REGIONS 审中-公开
    用于制造具有投影导电区域的选择性双极晶体管的电池阵列的方法

    公开(公告)号：US20090014709A1

    公开(公告)日：2009-01-15

    申请号：US12169452

    申请日：2008-07-08

    申请人： Fabio Pellizzer ,  Augusto Benvenuti ,  Paolo Cappelletti ,  Roberto Bez ,  Agostino Pirovano

    发明人： Fabio Pellizzer ,  Augusto Benvenuti ,  Paolo Cappelletti ,  Roberto Bez ,  Agostino Pirovano

    IPC分类号： H01L29/06 ,  H01L21/82

    CPC分类号： H01L27/1022 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

    摘要： A process manufactures an array of cells in a body of semiconductor material wherein a common conduction region of a first conductivity type and a plurality of shared control regions, of a second conductivity type, are formed in the body. The shared control regions extend on the common conduction region and are laterally delimited by insulating regions. Then, a grid-like layer is formed on the body to delimit a first plurality of empty regions directly overlying the body and conductive regions of semiconductor material and the first conductivity type are formed by filling the first plurality of empty regions, each conductive region forming, together with the common conduction region and an own shared control region, a bipolar junction transistor.

    摘要翻译： 一种方法制造半导体材料体中的单元阵列，其中在体内形成有第二导电类型的共同导电区域和多个第二导电类型的共用控制区域。 共享控制区域在公共导电区域上延伸并由绝缘区域侧向限定。 然后，在主体上形成网状层，以界定直接覆盖在主体和半导体材料的导电区域上的第一多个空区域，并且通过填充第一多个空区域形成第一导电类型，每个导电区域形成 与公共导电区域和自己的共用控制区域一起，双极结型晶体管。