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    Bi-directional read/program non-volatile floating gate memory array, and method of formation
    1.
    发明申请
    Bi-directional read/program non-volatile floating gate memory array, and method of formation 有权
    双向读/写非挥发性浮栅存储器阵列及其形成方法

    公开(公告)号：US20070069275A1

    公开(公告)日：2007-03-29

    申请号：US11239791

    申请日：2005-09-29

    申请人： Felix Tsui ,  Jeng-Wei Yang ,  Bomy Chen ,  Chun-Ming Chen ,  Dana Lee ,  Changyuan Chen

    发明人： Felix Tsui ,  Jeng-Wei Yang ,  Bomy Chen ,  Chun-Ming Chen ,  Dana Lee ,  Changyuan Chen

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336

    摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. An array of such memory cells comprises rows of cells in active regions adjacent to one another separated from one another by the semiconductive substrate material without any isolation material. Cells in the same column have the source/drain region in common, the drain/source region in common and a first and second control gates in each of the trenches in common. Cells in adjacent columns have the source/drain in common and the first control gate in common.

    摘要翻译： 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 控制栅极连接到每个源极/漏极区域，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。 这种存储单元的阵列包括彼此相邻的活性区域中的细胞排，所述活性区域通过没有任何隔离材料的半导体衬底材料彼此分开。 相同列中的单元具有共同的源极/漏极区域，共同的漏极/源极区域以及每个沟槽中的第一和第二控制栅极共同。 相邻列中的单元具有共同的源极/漏极，第一个控制栅极共同。

    Bi-directional read/program non-volatile floating gate memory array, and method of formation
    2.
    发明授权
    Bi-directional read/program non-volatile floating gate memory array, and method of formation 有权
    双向读/写非挥发性浮栅存储器阵列及其形成方法

    公开(公告)号：US07358559B2

    公开(公告)日：2008-04-15

    申请号：US11239791

    申请日：2005-09-29

    申请人： Felix (Ying-Kit) Tsui ,  Jeng-Wei Yang ,  Bomy Chen ,  Chun-Ming Chen ,  Dana Lee ,  Changyuan Chen

    发明人： Felix (Ying-Kit) Tsui ,  Jeng-Wei Yang ,  Bomy Chen ,  Chun-Ming Chen ,  Dana Lee ,  Changyuan Chen

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336

    摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. An array of such memory cells comprises rows of cells in active regions adjacent to one another separated from one another by the semiconductive substrate material without any isolation material. Cells in the same column have the source/drain region in common, the drain/source region in common and a first and second control gates in each of the trenches in common. Cells in adjacent columns have the source/drain in common and the first control gate in common.

    摘要翻译： 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 控制栅极连接到每个源极/漏极区域，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。 这种存储单元的阵列包括彼此相邻的活性区域中的细胞排，所述活性区域通过没有任何隔离材料的半导体衬底材料彼此分开。 相同列中的单元具有共同的源极/漏极区域，共同的漏极/源极区域以及每个沟槽中的第一和第二控制栅极共同。 相邻列中的单元具有共同的源极/漏极，第一个控制栅极共同。

    Hybrid programming methods and systems for non-volatile memory storage elements
    3.
    发明授权
    Hybrid programming methods and systems for non-volatile memory storage elements 有权
    用于非易失性存储器存储元件的混合编程方法和系统

    公开(公告)号：US07961511B2

    公开(公告)日：2011-06-14

    申请号：US11535452

    申请日：2006-09-26

    申请人： Dana Lee ,  Yingda Dong ,  Changyuan Chen ,  Jeffrey Lutze

    发明人： Dana Lee ,  Yingda Dong ,  Changyuan Chen ,  Jeffrey Lutze

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

    摘要： A hybrid method of programming a non-volatile memory cell to a final programmed state is described. The method described is a more robust protocol suitable for reliably programming selected memory cells while eliminating programming disturbs. The hybrid method comprises programming the non-volatile memory cell to a first state according to a first coarse programming mechanism, and programming the non-volatile memory cell according to a second different more precise programming mechanism thereby completing the programming of the non-volatile memory cell to the final programmed state. Additionally, the described method is particularly advantageous for programming multilevel chips.

    摘要翻译： 描述了将非易失性存储器单元编程到最终编程状态的混合方法。 所描述的方法是一种更鲁棒的协议，适用于可靠地编程所选择的存储器单元，同时消除编程干扰。 混合方法包括根据第一粗略编程机制将非易失性存储器单元编程为第一状态，以及根据第二种不同的更精确的编程机制对非易失性存储器单元进行编程，由此完成非易失性存储器的编程 单元格到最终编程状态。 另外，所描述的方法对于编程多级芯片是特别有利的。

    Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture
    4.
    发明授权
    Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture 有权
    非扩散结分离栅极非易失性存储器单元和阵列，其编程，擦除和读取方法以及制造方法

    公开(公告)号：US07723774B2

    公开(公告)日：2010-05-25

    申请号：US11775851

    申请日：2007-07-10

    申请人： Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

    发明人： Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

    IPC分类号： H01L29/788

    CPC分类号： G11C16/0458 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7887

    摘要： Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

    摘要翻译： 公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。 多个浮动栅极彼此间隔开并且与沟道区域绝缘。 多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。 多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。 通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

    Integrated Semiconductor Metal-Insulator-Semiconductor Capacitor
    5.
    发明申请
    Integrated Semiconductor Metal-Insulator-Semiconductor Capacitor 审中-公开
    集成半导体金属绝缘体 - 半导体电容器

    公开(公告)号：US20090096507A1

    公开(公告)日：2009-04-16

    申请号：US12270604

    申请日：2008-11-13

    申请人： Feng Gao ,  Changyuan Chen ,  Vishal Sarin ,  William John Saiki ,  Hieu Van Tran ,  Dana Lee

    发明人： Feng Gao ,  Changyuan Chen ,  Vishal Sarin ,  William John Saiki ,  Hieu Van Tran ,  Dana Lee

    IPC分类号： H03K3/01

    CPC分类号： H01L27/0805 ,  H01L27/0811 ,  H01L29/94

    摘要： An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.

    摘要翻译： 集成的MIS电容器具有两个基本相同的MIS电容器。 第一电容器包括在半导体衬底中与第一导电类型的沟道区相邻的第一导电类型的第一区域。 半导体衬底具有第二导电类型。 栅电极与第一电容器的沟道区隔离并隔开。 第二电容器基本上与第一电容器相同，并且形成在相同的半导体衬底中。 第一电容器的栅电极电连接到第二电容器的第一区域，并且第二电容器的栅极电连接到第一电容器的第一区域。 以这种方式，电容器以反并联配置连接。 具有高电容密度，低工艺复杂性，双极性操作，低电压和温度系数，低外部寄生电阻和电容以及用于可与现有半导体工艺结合的模拟设计的良好匹配特性的电容器。

    NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE
    10.
    发明申请
    NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE 有权
    非扩散结分离门非易失性记忆细胞和阵列，其编程，消除和阅读方法及其制造方法

    公开(公告)号：US20100220533A1

    公开(公告)日：2010-09-02

    申请号：US12773811

    申请日：2010-05-04

    申请人： Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

    发明人： Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

    IPC分类号： G11C16/04 ,  H01L29/788 ,  G11C16/16

    CPC分类号： G11C16/0458 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7887

    摘要： Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

    摘要翻译： 公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。 多个浮动栅极彼此间隔开并且与沟道区域绝缘。 多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。 多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。 通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。