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公开(公告)号：US5926059A
公开(公告)日：1999-07-20
申请号：US927391
申请日：1997-08-27
摘要： The invention relates to a voltage multiplier such as a charge pump circuit. The circuit is realized by a plurality of cascade connected voltage gain stages, each stage comprising a first and a second cell each receiving a pair of clock phase signals and comprising a pair of MOS transistors having first and second conduction terminals and a control terminal. These transistors have their first conduction terminals connected together and to a voltage reference; while the control terminals of each transistor are connected to the second conduction terminal of the other transistor of the same cell. Moreover, the second conduction terminal of the first transistor receives a first phase signal via a first coupling capacitor, and the second conduction terminal of the second transistor receives a second phase signals via a first pumping capacitor. Third and fourth cells are provided having the same structure as the first and the second cell. The third cell is coupled to the first cell by a series connection between their corresponding coupling capacitors and their corresponding pumping capacitors, respectively. The fourth cell is coupled to the second cell by a series connection between their corresponding coupling capacitors and by their corresponding pumping capacitors, respectively.
摘要翻译： 本发明涉及诸如电荷泵电路的电压倍增器。 电路由多个级联连接的电压增益级实现，每级包括第一和第二单元，每个单元接收一对时钟相位信号，并且包括一对具有第一和第二导通端子的MOS晶体管和控制端子。 这些晶体管的第一导通端子连接在一起并连接到电压基准上; 而每个晶体管的控制端子连接到同一单元的另一个晶体管的第二导电端子。 此外，第一晶体管的第二导通端子经由第一耦合电容器接收第一相位信号，并且第二晶体管的第二导通端子经由第一泵浦电容器接收第二相位信号。 提供具有与第一和第二电池相同结构的第三和第四电池。 第三单元通过其相应的耦合电容器和它们相应的泵浦电容器之间的串联连接耦合到第一单元。 第四单元通过它们对应的耦合电容器和它们相应的泵浦电容器之间的串联连接耦合到第二单元。
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2.发明授权Electrically erasable and programmable non-volatile memory device with testable redundancy circuits 失效具有可测试冗余电路的电可擦除和可编程非易失性存储器件
公开(公告)号：US5999450A
公开(公告)日：1999-12-07
申请号：US853756
申请日：1997-05-08
申请人： Marco Dallabora , Corrado Villa , Marco Defendi
发明人： Marco Dallabora , Corrado Villa , Marco Defendi
摘要： An electrically erasable and programmable non-volatile memory device comprises at least one memory sector comprising an array of memory cells arranged in rows and first-level columns, the first-level columns being grouped together in groups of first-level columns each coupled to a respective second-level column, first-level selection means for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means for selecting one of the second-level columns, first direct memory access test means activatable in a first test mode for directly coupling a selected memory cell of the array to a respective output terminal of the memory device, redundancy columns of redundancy memory cells for replacing defective columns of memory cells, and a redundancy control circuit comprising defective-address storage means for storing addresses of the defective columns and activating respective redundancy columns when the defective columns are addressed. The redundancy control circuit comprises second direct memory access test means activatable in a second test mode together with the first direct memory access test means for directly coupling memory elements of the defective-address storage means to respective second-level columns of the array, whereby the memory elements of the defective-address storage means can be directly coupled to output terminals of the memory device.
摘要翻译： 电可擦除和可编程的非易失性存储器件包括至少一个存储器扇区，其包括排列成行和第一级列的存储器单元的阵列，所述第一级列按第一级列分组在一起，每一列耦合到 相应的第二级列，用于将每个组的一个第一级列选择性地耦合到相应的第二级列的第一级选择装置，用于选择第二级列之一的第二级选择装置，第一直接存储器访问测试 意味着可以在第一测试模式中激活，用于将阵列的所选择的存储单元直接耦合到存储器件的相应输出端，冗余存储单元的冗余列用于替换存储单元的有缺陷的列，以及冗余控制电路，包括缺陷地址 存储装置，用于存储有缺陷列的地址，并在添加有缺陷列时激活相应的冗余列 退缩 冗余控制电路包括与第一直接存储器存取测试装置一起在第二测试模式下激活的第二直接存储器访问测试装置，用于将缺陷地址存储装置的存储元件直接耦合到阵列的相应第二级列，由此 缺陷地址存储装置的存储元件可以直接耦合到存储器件的输出端。
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3.发明授权Method of programming a nonvolatile flash-EEPROM memory array using source line switching transistors 失效使用源极线开关晶体管编程非易失性闪存EEPROM存储器阵列的方法
公开(公告)号：US5633822A
公开(公告)日：1997-05-27
申请号：US458346
申请日：1995-06-02
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C16/30 , H01L21/8247 , H01L27/115 , G11C16/02
CPC分类号： G11C16/04 , G11C16/0416 , G11C16/30
摘要： A method for writing cells in a memory which reduces errors caused by depleted memory array cells being turned on even when not selected. In the method, nonselected bit lines and nonselected word lines are biased so that the threshold voltage of the nonselected cells increases. In particular, the nonselected bit lines are left floating and the nonselected word lines are set to a zero voltage. Appropriate potentials are applied to the selected word line, selected bit line, and selected source line in order to program the selected cell.
摘要翻译： 一种用于将存储器中的单元写入的方法，其减少由耗尽的存储器阵列单元导致的错误，即使在未选择的情况下也被导通。 在该方法中，非选择位线和非选择字线被偏置，使得非选择单元的阈值电压增加。 特别地，非选定的位线保持浮动，并且非选择的字线被设置为零电压。 适当的电位被施加到所选择的字线，所选位线和所选择的源极线以便对所选择的单元进行编程。
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公开(公告)号：US5784314A
公开(公告)日：1998-07-21
申请号：US679656
申请日：1996-07-12
申请人： Mauro Sali , Marco Dallabora , Marcello Carrera
发明人： Mauro Sali , Marco Dallabora , Marcello Carrera
CPC分类号： G11C16/3459 , G11C16/3454 , G11C29/028 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/5006
摘要： A method for setting the threshold voltage of a reference memory cell of a memory device is described, the reference memory cell being used as a reference current generator for generating a reference current which is compared by a sensing circuit of the memory device with currents sunk by memory cells to be sensed, belonging to a memory matrix of the memory device. The method comprises a first step in which the reference memory cell is submitted to a change in its threshold voltage, and a second step in which the threshold voltage of the reference memory cell is verified. The second step provides for performing a sensing of the reference memory cell using a memory cell with known threshold voltage belonging to the memory matrix as a reference current generator for generating a current which is compared by the sensing circuit with the current sunk by the reference memory cell.
摘要翻译： 描述了一种用于设置存储器件的参考存储单元的阈值电压的方法，该参考存储器单元用作参考电流发生器，用于产生参考电流，该参考电流由存储器件的感测电路与下降的电流进行比较 要被感测的存储器单元，属于存储器件的存储器矩阵。 该方法包括第一步骤，其中参考存储器单元被提交其阈值电压的改变，以及第二步骤，其中验证参考存储单元的阈值电压。 第二步骤是使用具有属于存储器矩阵的已知阈值电压的存储单元作为参考电流发生器来执行对参考存储单元的感测，用于产生电流，该电流由感测电路与当前由参考存储器 细胞。
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5.发明授权Method of reading, erasing and programming a nonvolatile flash-EEPROM memory arrray using source line switching transistors 失效使用源极线开关晶体管读取，擦除和编程非易失性闪存EEPROM存储器的方法
公开(公告)号：US5587946A
公开(公告)日：1996-12-24
申请号：US212907
申请日：1994-03-15
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C16/30 , H01L21/8247 , H01L27/115 , G11C16/02
CPC分类号： G11C16/04 , G11C16/0416 , G11C16/30
摘要： To reduce read and write errors caused by depleted memory array cells being turned on even when not selected, the nonselected memory cells are so biased as to present a floating terminal and a terminal at a positive voltage with respect to the substrate region. The threshold voltage of nonselected cells (i.e., the minimum voltage between the gate and source terminals for the cell to be turned on) increases due to a "body effect", whereby the threshold voltage depends on the voltage drop between the source terminal and the substrate. The source line of a selected cell is biased to a positive value greater than that of the bit line of the selected cell. Methods for reading, writing and erasing cells using certain voltage levels are disclosed.
摘要翻译： 为了减少由于耗尽的存储器阵列单元即使未被选择而导通的读取和写入错误，非选择的存储器单元被偏置以使浮动端子和端子相对于衬底区域处于正电压。 非选择单元的阈值电压（即，用于导通的单元的栅极和源极端子之间的最小电压）由于“体效应”而增加，由此阈值电压取决于源极端子与源极端子之间的电压降 基质。 所选单元格的源极线被偏置为大于所选单元的位线的正值。 公开了使用特定电压电平读取，写入和擦除单元的方法。
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公开(公告)号：US5258959A
公开(公告)日：1993-11-02
申请号：US810480
申请日：1991-12-19
申请人： Marco Dallabora , Corrado Villa
发明人： Marco Dallabora , Corrado Villa
CPC分类号： G11C16/28
摘要： A memory cell reading circuit has a reference cell bit line and a matrix cell bit line connected to a supply voltage through respective loads and are furthermore connected by normally-off equalization transistors which are enabled by a first clock signal. The bit lines are further connected by normally-off resistive equalization transistors whose resistance is significant in conducting conditions. The equalization transistors are enabled by a first clock signal and the resistive equalization transistors are enabled by a second clock signal which has a duration that extends longer than the first clock signal. The memory cell reading circuit decreases the "read" time required for a memory cell, such as an EPROM cell, as compared to reading circuits previously used.
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7.发明授权Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells 有权用于读取和验证电可编程/可擦除非易失性存储单元的内容的感测电路
公开(公告)号：US6055187A
公开(公告)日：2000-04-25
申请号：US209319
申请日：1998-12-09
摘要： A sense amplifier circuit for reading and verifying the contents of non-volatile memory cells in a semiconductor integrated device including a memory matrix of electrically programmable and erasable cells. The circuit includes a sense amplifier which has a first input connected to a reference load column incorporating a reference cell, and a second input connected to a second matrix load column incorporating a cell of the memory matrix. The circuit also includes a small matrix of reference cells connected, in parallel with one another, in the reference load column. Also provided is a double current mirror having a first mirror column which is connected to a node in the reference load column connected to the first input, and a second mirror column coupled to the second matrix load column to locally replicate, on the second mirror column, the electric potential at the node during a load equalizing step.
摘要翻译： 一种用于读取和验证包括电可编程和可擦除单元的存储矩阵的半导体集成器件中的非易失性存储单元的内容的读出放大器电路。 该电路包括一个读出放大器，该读出放大器的第一输入端连接到一个结合有参考单元的参考负载列，以及一个第二输入端，连接到一个结合存储矩阵单元的第二矩阵负载列。 电路还包括在参考负载列中彼此并联连接的参考单元的小矩阵。 还提供了双电流镜，其具有连接到连接到第一输入的参考负载列中的节点的第一反射镜列和耦合到第二矩阵负载列的第二反射镜列，以在第二反射镜列上局部复制 ，负载平衡步骤期间节点处的电位。
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8.发明授权Sectorized electrically erasable and programmable non-volatile memory device with redundancy 失效具有冗余性的扇区式电可擦除和可编程非易失性存储器件
公开(公告)号：US5854764A
公开(公告)日：1998-12-29
申请号：US821804
申请日：1997-03-21
CPC分类号： G11C29/82
摘要： A sectorized electrically erasable and programmable non-volatile memory device comprises: a plurality of individually-addressable memory sectors, each memory sector comprising an array of memory cells arranged in rows and columns; redundancy columns of redundancy memory cells for replacing defective columns of memory cells; and a redundancy control circuit for storing addresses of the defective columns and activating respective redundancy columns when said defective columns are addressed. Each memory sector comprises at least one respective redundancy column. The redundancy control circuit comprises at least one memory means comprising individually addressable memory locations each one associated with a respective memory sector for storing, individually for each memory sector, addresses of a defective column belonging to the memory sector, and an address recognition means associated with said memory means for recognizing if a current address supplied to the memory device coincides with a defective column address stored in an addressed one of said memory locations associated with a currently addressed memory sector.
摘要翻译： 扇区化的电可擦除和可编程的非易失性存储器设备包括：多个可单独寻址的存储器扇区，每个存储器扇区包括以行和列布置的存储器单元的阵列; 用于替换存储器单元的有缺陷的列的冗余存储单元的冗余列; 以及冗余控制电路，用于存储所述缺陷列的地址，并且当所述缺陷列被寻址时激活相应的冗余列。 每个存储器扇区包括至少一个相应的冗余列。 冗余控制电路包括至少一个存储器装置，其包括单独可寻址的存储器位置，每个存储器位置与相应的存储器扇区相关联，每个存储器单元分别存储针对每个存储器扇区的属于存储器扇区的缺陷列的地址，以及与 所述存储器装置用于识别提供给存储器件的当前地址是否与存储在与当前寻址的存储器扇区相关联的所述存储器位置中的所寻址的一个存储器中的有缺陷的列地址一致。
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公开(公告)号：US5638327A
公开(公告)日：1997-06-10
申请号：US412162
申请日：1995-03-28
IPC分类号： H01L21/8247 , G11C16/04 , G11C16/16 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/00
CPC分类号： G11C16/16 , G11C16/0416 , H01L27/115 , H01L29/7885
摘要： A flash-EEPROM memory array presenting a NOR architecture wherein the memory cells, organized in rows and columns and having drain regions connected to respective bit lines, source regions connected to a common source line, and control gate regions connected to respective word lines, present an asymmetrical structure wherein one of the source and drain regions presents a highly resistive portion to permit programming and erasing of the cells at different regions. The array includes bias transistors arranged in a row and each connected between a respective bit line and the common source line, for maintaining at the same potential the drain and source regions of the cells connected to the nonaddressed bit lines during programming, and so preventing spurious writing.
摘要翻译： 呈现NOR架构的闪存EEPROM存储器阵列，其中以行和列组织并且具有连接到相应位线的漏极区域，连接到公共源极线路的源极区域和连接到相应字线的控制栅极区域的存储器单元呈现 不对称结构，其中源区和漏区之一呈现高电阻部分，以允许在不同区域对单元进行编程和擦除。 该阵列包括排列成一行并且各自连接在相应的位线和公共源极线之间的偏置晶体管，用于在编程期间将连接到非寻址位线的单元的漏极和源极区域保持在相同的电位，从而防止杂散 写作。
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10.发明授权
公开(公告)号：US5179300A
公开(公告)日：1993-01-12
申请号：US691768
申请日：1991-04-26
申请人： Paolo Rolandi , Marco Dallabora , Marco Maccalli
发明人： Paolo Rolandi , Marco Dallabora , Marco Maccalli
IPC分类号： H03K19/0185 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00361
摘要： A data output stage of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors associated to drive an output node of said stage, comprises first and second feedback loops which are structurally independent and respectively connected between said node and a corresponding gate electrode of each transistor to precharge said output node at a predetermined value and reduce the noise to ground during the switching phase.
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