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    Integrated circuit passive signal distribution
    1.
    发明授权
    Integrated circuit passive signal distribution 有权
    集成电路无源信号分配

    公开(公告)号：US08571513B2

    公开(公告)日：2013-10-29

    申请号：US13540500

    申请日：2012-07-02

    申请人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

    发明人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

    IPC分类号： H04B1/28

    CPC分类号： H04L25/0278 ,  H03K5/15013 ,  H04L25/0292 ,  H04L25/0298

    摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。

    INTEGRATED CIRCUIT PASSIVE SIGNAL DISTRIBUTION
    2.
    发明申请
    INTEGRATED CIRCUIT PASSIVE SIGNAL DISTRIBUTION 有权
    集成电路被动信号分配

    公开(公告)号：US20120281323A1

    公开(公告)日：2012-11-08

    申请号：US13540500

    申请日：2012-07-02

    申请人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

    发明人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

    IPC分类号： H02H9/04

    CPC分类号： H04L25/0278 ,  H03K5/15013 ,  H04L25/0292 ,  H04L25/0298

    摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。

    Integrated circuit passive signal distribution
    3.
    发明授权
    Integrated circuit passive signal distribution 有权
    集成电路无源信号分配

    公开(公告)号：US08213894B2

    公开(公告)日：2012-07-03

    申请号：US11323370

    申请日：2005-12-29

    申请人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

    发明人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

    IPC分类号： H04B1/28

    CPC分类号： H04L25/0278 ,  H03K5/15013 ,  H04L25/0292 ,  H04L25/0298

    摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。

    Forwarded clock filtering
    6.
    发明授权
    Forwarded clock filtering 有权
    转发时钟滤波

    公开(公告)号：US07573326B2

    公开(公告)日：2009-08-11

    申请号：US11323310

    申请日：2005-12-30

    申请人： Bryan K. Casper ,  Timothy Hollis ,  James E. Jaussi ,  Stephen R. Mooney ,  Frank O'Mahony ,  Mozhgan Mansuri

    发明人： Bryan K. Casper ,  Timothy Hollis ,  James E. Jaussi ,  Stephen R. Mooney ,  Frank O'Mahony ,  Mozhgan Mansuri

    IPC分类号： H03B1/00

    CPC分类号： H03K5/1565 ,  H03H11/1291 ,  H03K5/01 ,  H03K5/1252 ,  H04L7/027

    摘要： A tunable bandpass filter to provide a filtered differential clock signal in response to an input differential clock signal, where an embodiment comprises a transistor pair loaded by tunable loads, and a feedback circuit to tune the tunable loads. In some embodiments, the feedback circuit tunes the loads to maximize a small-signal differential gain. In other embodiments, the feedback circuit tunes the loads to minimize a metric indicative of jitter in the filtered differential clock signal. Other embodiments are described and claimed.

    摘要翻译： 一种可调谐带通滤波器，用于响应于输入差分时钟信号提供经滤波的差分时钟信号，其中实施例包括由可调谐负载加载的晶体管对，以及用于调谐可调负载的反馈电路。 在一些实施例中，反馈电路调谐负载以最大化小信号差分增益。 在其他实施例中，反馈电路调整负载以最小化指示经滤波的差分时钟信号中的抖动的度量。 描述和要求保护其他实施例。

    Simultaneous transmission and reception of signals in different frequency bands over a bus line
    7.
    发明授权
    Simultaneous transmission and reception of signals in different frequency bands over a bus line 有权
    在总线上同时发送和接收不同频段的信号

    公开(公告)号：US07177288B2

    公开(公告)日：2007-02-13

    申请号：US09998008

    申请日：2001-11-28

    申请人： Stephen R. Mooney ,  Aaron K. Martin ,  Matthew B. Haycock ,  Bryan K. Casper ,  Shekhar Y. Borkar ,  Joseph T. Kennedy ,  James E. Jaussi

    发明人： Stephen R. Mooney ,  Aaron K. Martin ,  Matthew B. Haycock ,  Bryan K. Casper ,  Shekhar Y. Borkar ,  Joseph T. Kennedy ,  James E. Jaussi

    IPC分类号： H04L5/14

    CPC分类号： H04L5/1423

    摘要： A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.

    摘要翻译： 一种设备包括总线，连接到总线的第一发射机，并且被配置为在第一频带中通过总线传输第一信号，第二发射器连接到总线并且被配置为以第二频率通过总线发送第二信号 与第一发射机正在发送第一信号的同时，连接到总线并被配置为接收通过总线在第一频带中发送的第一信号的第一接收机和连接到总线的第二接收机，并且被配置为 接收在第二频带中通过总线发送的第二信号。 第一频带和第二频带占据频谱的不同部分。

    Voltage margin testing of a transmission line analog signal using a variable offset comparator in a data receiver circuit
    8.
    发明授权
    Voltage margin testing of a transmission line analog signal using a variable offset comparator in a data receiver circuit 失效
    在数据接收器电路中使用可变偏移比较器的传输线模拟信号的电压裕度测试

    公开(公告)号：US06653893B2

    公开(公告)日：2003-11-25

    申请号：US09967666

    申请日：2001-09-28

    申请人： Bryan K. Casper ,  Stephen R. Mooney ,  Matthew B. Haycock

    发明人： Bryan K. Casper ,  Stephen R. Mooney ,  Matthew B. Haycock

    IPC分类号： H03F345

    CPC分类号： H03F3/45183 ,  H03F3/45672 ,  H03F2203/45371

    摘要： A data receiver circuit having a comparator that exhibits substantially variable offset that is controllable to represent a variable reference level, without a separate input to receive a reference voltage level. The comparator output provides an indication of the comparison between a fixed voltage level applied to its differential signal input and the variable reference level. While changing an offset code that is fed to an offset control input of the comparator, and while applying a fixed voltage level that represents a symbol in the transmission line analog signal, a value of the offset code which causes the output of the comparator to change states is captured. A similar process may be repeated for different symbol values that can be transmitted, such that an indication of the voltage margin may be obtained as a difference between two captured offset codes. Circuitry to perform the process may be provided on-chip to the receiver circuit.

    摘要翻译： 一种具有比较器的数据接收器电路，其具有可变的偏移，其可控制以表示可变参考电平，而没有单独的输入以接收参考电压电平。 比较器输出提供了施加到其差分信号输入的固定电压电平与可变参考电平之间的比较的指示。 在改变馈送到比较器的偏移控制输入的偏移代码的同时，在施加表示传输线模拟信号中的符号的固定电压电平的同时，使比较器的输出变化的偏移代码的值 状态被捕获。 可以对可以发送的不同符号值重复类似的过程，使得可以获得电压余量的指示作为两个所捕获的偏移码之间的差。 执行该处理的电路可以片上提供给接收器电路。

    Using a timing strobe for synchronization and validation in a digital logic device
    9.
    发明授权
    Using a timing strobe for synchronization and validation in a digital logic device 有权
    在数字逻辑器件中使用定时选通器进行同步和验证

    公开(公告)号：US06437601B1

    公开(公告)日：2002-08-20

    申请号：US09752906

    申请日：2000-12-26

    申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： H03K19096

    CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/00 ,  H03L7/0812 ,  H04L7/0008

    摘要： In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.

    摘要翻译： 在具有第一和第二逻辑器件的电子系统中，由第一逻辑器件产生自由运行的片上时钟信号，其中信号的频率被控制以匹配由两者接收的全局自由运行时钟信号的频率 设备。 片上时钟信号与第一器件接收的选通信号同步，并与第二器件与数据信号相关联地发送。 重复执行由第一时钟信号同步的逻辑功能，以从数据信号重复产生一个或多个位。

    Biased control loop circuit for setting impedance of output driver
    10.
    发明授权
    Biased control loop circuit for setting impedance of output driver 有权
    用于设置输出驱动器阻抗的偏置控制回路电路

    公开(公告)号：US06424175B1

    公开(公告)日：2002-07-23

    申请号：US09659499

    申请日：2000-09-11

    申请人： Sriram R. Vangal ,  Matthew B. Haycock ,  Stephen R. Mooney

    发明人： Sriram R. Vangal ,  Matthew B. Haycock ,  Stephen R. Mooney

    IPC分类号： H03K1716

    CPC分类号： H03K19/00384

    摘要： A biased control loop for setting the impedance of an output driver includes a dummy driver having a variable output impedance, a sample and compare circuit to compare the output impedance of dummy output driver to a reference, and an up/down counter to modify the impedance. When the loop is locked, an error signal alternates positive and negative about a reference value. A digital filter produces a filtered version of the error signal with an apparent error value that does not alternate. The digital filter has a biased lock circuit that guarantees that the apparent error does not alternate. A simultaneous bidirectional port includes an output driver and the biased control loop to set the output driver impedance. When the output driver drives a bidirectional line and serves as a termination impedance for another driver, the reduced apparent error variation provides improved impedance matching.

    摘要翻译： 用于设置输出驱动器的阻抗的偏置控制环路包括具有可变输出阻抗的虚拟驱动器，用于将虚拟输出驱动器的输出阻抗与参考值进行比较的采样和比较电路以及用于修改阻抗的上/下计数器 。 当环路被锁定时，错误信号会围绕参考值交替正负。 数字滤波器产生误差信号的滤波版本，具有不交替的明显误差值。 数字滤波器具有偏置的锁定电路，保证视在误差不会交替。 同时双向端口包括输出驱动器和偏置控制环路以设置输出驱动器阻抗。 当输出驱动器驱动双向线并用作另一个驱动器的终端阻抗时，减小的视差误差提供改进的阻抗匹配。