公开(公告)号：US08084865B2

公开(公告)日：2011-12-27

申请号：US12112588

申请日：2008-04-30

申请人： Franz Hirler ,  Walter Rieger ,  Uwe Schmalzbauer ,  Rudolf Zelsacher ,  Markus Zundel

发明人： Franz Hirler ,  Walter Rieger ,  Uwe Schmalzbauer ,  Rudolf Zelsacher ,  Markus Zundel

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L29/7813 ,  H01L21/743 ,  H01L23/535 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure.

摘要翻译： 用于半导体器件的金属结构的锚定结构包括具有至少一个悬垂侧壁的锚固凹槽结构，金属结构至少部分地布置在锚定凹槽结构内。

公开(公告)号：US20080265427A1

公开(公告)日：2008-10-30

申请号：US12112588

申请日：2008-04-30

申请人： Franz Hirler ,  Walter Rieger ,  Uwe Schmalzbauer ,  Rudolf Zelsacher ,  Markus Zundel

发明人： Franz Hirler ,  Walter Rieger ,  Uwe Schmalzbauer ,  Rudolf Zelsacher ,  Markus Zundel

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L29/7813 ,  H01L21/743 ,  H01L23/535 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure.

摘要翻译： 用于半导体器件的金属结构的锚定结构包括具有至少一个悬垂侧壁的锚固凹槽结构，金属结构至少部分地布置在锚定凹槽结构内。

公开(公告)号：US08933448B2

公开(公告)日：2015-01-13

申请号：US13560897

申请日：2012-07-27

申请人： Markus Zundel ,  Uwe Schmalzbauer

发明人： Markus Zundel ,  Uwe Schmalzbauer

IPC分类号： H01L23/58

CPC分类号： H01L21/78 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Wafers with chips thereon and corresponding chips are provided where test structures or parts thereof are provided in a peripheral chip area of the chip. Corresponding methods are also disclosed.

摘要翻译： 提供具有芯片的晶片和相应的芯片，其中测试结构或其部分设置在芯片的外围芯片区域中。 还公开了相应的方法。

公开(公告)号：US08803297B2

公开(公告)日：2014-08-12

申请号：US13571462

申请日：2012-08-10

申请人： Peter Nelle ,  Uwe Schmalzbauer ,  Juergen Holzmueller ,  Markus Zundel

发明人： Peter Nelle ,  Uwe Schmalzbauer ,  Juergen Holzmueller ,  Markus Zundel

IPC分类号： H01L23/58

CPC分类号： H01L21/02359 ,  H01L21/02129 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/78 ,  H01L23/29 ,  H01L23/3192 ,  H01L23/562 ,  H01L29/0603 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a main body having a single crystalline semiconductor body. A layered structure directly adjoins a central portion of a main surface of the main body and includes a hard dielectric layer provided from a first dielectric material with Young's modulus greater than 10 GPa. A stress relief layer directly adjoins the layered structure opposite to the main body and extends beyond an outer edge of the layered structure. Providing the layered structure at a distance to the edge of the main body and covering the outer surface of the layered structures with the stress relief layer enhances device reliability.

摘要翻译： 半导体器件包括具有单晶半导体本体的主体。 分层结构直接毗邻主体的主表面的中心部分，并且包括由杨氏模量大于10GPa的第一介电材料提供的硬电介质层。 应力消除层直接邻接与主体相对的分层结构，并且延伸超过层状结构的外边缘。 通过提供与主体边缘一定距离的层状结构并且用应力释放层覆盖层状结构的外表面增强了设备的可靠性。

公开(公告)号：US07939885B2

公开(公告)日：2011-05-10

申请号：US12112547

申请日：2008-04-30

申请人： Mathias Hans-Ulrich Alexander Von Borcke ,  Markus Zundel ,  Uwe Schmalzbauer

发明人： Mathias Hans-Ulrich Alexander Von Borcke ,  Markus Zundel ,  Uwe Schmalzbauer

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7815

摘要： A semiconductor device has a substrate having a plurality of neighboring trenches, and a contact area, one mesa stripe each being formed between two neighboring trenches. The contact area contacts mesa stripes and surrounds an opening region in which the contact area is not formed and which is formed such that the contact area contacts the same mesa stripes at two positions between which the opening region is arranged, and the opening region having a region of elongate extension which intersects the mesa stripes in a skewed or perpendicular manner.

摘要翻译： 半导体器件具有具有多个相邻沟槽的衬底，以及每个在两个相邻沟槽之间形成的接触区域，一个台面条纹。 接触区域接触台面条状并且围绕其中未形成接触区域的开口区域，并且其形成为使得接触区域在布置有开口区域的两个位置处接触相同的台面条纹，并且开口区域具有 细长延伸区域以斜面或垂直方式与台面条纹相交。

公开(公告)号：US07800171B2

公开(公告)日：2010-09-21

申请号：US11870750

申请日：2007-10-11

申请人： Mathias Von Borcke ,  Markus Zundel ,  Thorsten Meyer ,  Uwe Schmalzbauer

发明人： Mathias Von Borcke ,  Markus Zundel ,  Thorsten Meyer ,  Uwe Schmalzbauer

IPC分类号： H01L21/336

CPC分类号： H01L29/7815 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7811 ,  H01L29/7813 ,  H03K17/18 ,  H03K17/687

摘要： An integrated circuit including a semiconductor device is disclosed. One embodiment provides a load current component, having a multiplicity of trenches in a cell array. A sensor component is integrated into the cell array of the load current component and has a sensor cell array, the area of which is smaller than the area of the cell array of the load current component by a specific factor. The trenches forming the cell array of the sensor component correspond to the trenches of the cell array of the load current component, configured such that the trenches of the sensor component at the at least one side merge uniformly into the trenches of the cell array of the load current component without interruptions or disturbances of the trench geometry.

摘要翻译： 公开了一种包括半导体器件的集成电路。 一个实施例提供负载电流分量，其具有单元阵列中的多个沟槽。 传感器组件被集成到负载电流分量的单元阵列中，并且具有传感器单元阵列，其区域小于负载电流分量的单元阵列的面积的特定因子。 形成传感器组件的单元阵列的沟槽对应于负载电流分量的单元阵列的沟槽，其被配置为使得至少一侧的传感器组件的沟槽均匀地合并到单元阵列的沟槽中 负载电流分量，不影响沟槽几何形状的干扰或干扰。

公开(公告)号：US20080296668A1

公开(公告)日：2008-12-04

申请号：US12112547

申请日：2008-04-30

申请人： Mathias Hans-Ulrich Alexander Von Borcke ,  Markus Zundel ,  Uwe Schmalzbauer

发明人： Mathias Hans-Ulrich Alexander Von Borcke ,  Markus Zundel ,  Uwe Schmalzbauer

IPC分类号： H01L29/06 ,  H01L29/02 ,  H01L21/44 ,  H01L21/02

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7815

摘要： A semiconductor device has a substrate having a plurality of neighboring trenches, and a contact area, one mesa stripe each being formed between two neighboring trenches. The contact area contacts mesa stripes and surrounds an opening region in which the contact area is not formed and which is formed such that the contact area contacts the same mesa stripes at two positions between which the opening region is arranged, and the opening region having a region of elongate extension which intersects the mesa stripes in a skewed or perpendicular manner.

摘要翻译： 半导体器件具有具有多个相邻沟槽的衬底，以及每个在两个相邻沟槽之间形成的接触区域，一个台面条纹。 接触区域接触台面条状并且围绕其中未形成接触区域的开口区域，并且其形成为使得接触区域在布置有开口区域的两个位置处接触相同的台面条纹，并且开口区域具有 细长延伸区域以斜面或垂直方式与台面条纹相交。

公开(公告)号：US20140042597A1

公开(公告)日：2014-02-13

申请号：US13571462

申请日：2012-08-10

申请人： Peter Nelle ,  Uwe Schmalzbauer ,  Juergen Holzmueller ,  Markus Zundel

发明人： Peter Nelle ,  Uwe Schmalzbauer ,  Juergen Holzmueller ,  Markus Zundel

IPC分类号： H01L29/06 ,  H01L21/02

CPC分类号： H01L21/02359 ,  H01L21/02129 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/78 ,  H01L23/29 ,  H01L23/3192 ,  H01L23/562 ,  H01L29/0603 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a main body having a single crystalline semiconductor body. A layered structure directly adjoins a central portion of a main surface of the main body and includes a hard dielectric layer provided from a first dielectric material with Young's modulus greater than 10 GPa. A stress relief layer directly adjoins the layered structure opposite to the main body and extends beyond an outer edge of the layered structure. Providing the layered structure at a distance to the edge of the main body and covering the outer surface of the layered structures with the stress relief layer enhances device reliability.

摘要翻译： 半导体器件包括具有单晶半导体本体的主体。 分层结构直接毗邻主体的主表面的中心部分，并且包括由杨氏模量大于10GPa的第一介电材料提供的硬电介质层。 应力消除层直接邻接与主体相对的分层结构，并且延伸超过层状结构的外边缘。 通过提供与主体边缘一定距离的层状结构并且用应力释放层覆盖层状结构的外表面增强了设备的可靠性。

公开(公告)号：US20080088355A1

公开(公告)日：2008-04-17

申请号：US11870750

申请日：2007-10-11

申请人： Mathias Von Borcke ,  Markus Zundel ,  Thorsten Meyer ,  Uwe Schmalzbauer

发明人： Mathias Von Borcke ,  Markus Zundel ,  Thorsten Meyer ,  Uwe Schmalzbauer

IPC分类号： H03K17/687

CPC分类号： H01L29/7815 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7811 ,  H01L29/7813 ,  H03K17/18 ,  H03K17/687

摘要： An integrated circuit including a semiconductor device is disclosed. One embodiment provides a load current component, having a multiplicity of trenches in a cell array. A sensor component is integrated into the cell array of the load current component and has a sensor cell array, the area of which is smaller than the area of the cell array of the load current component by a specific factor. The trenches forming the cell array of the sensor component correspond to the trenches of the cell array of the load current component, configured such that the trenches of the sensor component at the at least one side merge uniformly into the trenches of the cell array of the load current component without interruptions or disturbances of the trench geometry.

摘要翻译： 公开了一种包括半导体器件的集成电路。 一个实施例提供负载电流分量，其具有单元阵列中的多个沟槽。 传感器组件被集成到负载电流分量的单元阵列中，并且具有传感器单元阵列，其区域小于负载电流分量的单元阵列的面积的特定因子。 形成传感器组件的单元阵列的沟槽对应于负载电流分量的单元阵列的沟槽，其被配置为使得至少一侧的传感器组件的沟槽均匀地合并到单元阵列的沟槽中 负载电流分量，不影响沟槽几何形状的干扰或干扰。