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    FEEDBACK SYSTEM INCORPORATING SLOW DIGITAL SWITCHING FOR GLITCH-FREE STATE CHANGES
    3.
    发明申请
    FEEDBACK SYSTEM INCORPORATING SLOW DIGITAL SWITCHING FOR GLITCH-FREE STATE CHANGES 有权
    无反馈状态变化的反馈系统兼容缓慢的数字切换

    公开(公告)号：US20070057736A1

    公开(公告)日：2007-03-15

    申请号：US11557091

    申请日：2006-11-06

    申请人： Rex Baird ,  Yunteng Huang ,  Michael Perrott

    发明人： Rex Baird ,  Yunteng Huang ,  Michael Perrott

    IPC分类号： H03L7/00

    CPC分类号： H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/0034 ,  H03L7/10 ,  H03L2207/06 ,  H04L7/033

    摘要： A feedback system such as a phase locked loop (PLL) includes a second feedback loop which responds when a VCO control voltage is near either end of its range, by slowly adjusting additional tuning elements which control the VCO frequency. The second feedback loop is arranged to cause a slow enough change in the VCO frequency that the first traditional feedback loop adjusts the control voltage quickly enough in a direction toward its mid-range value to keep the VCO frequency substantially unchanged. The second feedback loop advantageously incorporates one or more digital control signals which preferably change no more than one bit at a time and with a controlled slow ramp rate. As a result, the PLL maintains phase accuracy so that the operation of the PLL, including subtle specifications such as input data jitter tolerance or output jitter generation when used for clock and data recovery applications, is not negatively impacted. An impedance tuning feedback system provides a resistance between two nodes which is proportional to a reference resistance, and preferably incorporates slow digital switching to result in near perturbation-free state changes over the tuning range of the resistance.

    摘要翻译： 诸如锁相环（PLL）的反馈系统包括第二反馈环路，其通过缓慢调节控制VCO频率的附加调谐元件来响应VCO控制电压在其范围的任一端附近。 第二反馈环路被布置成使得VCO频率的足够慢的变化，使得第一传统反馈环路在朝向其中等范围值的方向上足够快地调节控制电压以保持VCO频率基本上不变。 第二反馈回路有利地结合了一个或多个数字控制信号，其优选地一次改变不超过一个位并且具有受控的缓慢的斜率。 因此，PLL保持相位精度，使得在用于时钟和数据恢复应用的情况下，包括诸如输入数据抖动容限或输出抖动产生等微妙规范的PLL的操作不会受到负面影响。 阻抗调谐反馈系统提供与参考电阻成比例的两个节点之间的电阻，并且优选地包括慢速数字开关以导致电阻的调谐范围附近的无扰动状态变化。

    Method and apparatus for reducing quantization noise in fractional-N frequency synthesizers
    4.
    发明申请
    Method and apparatus for reducing quantization noise in fractional-N frequency synthesizers 有权
    分数N频率合成器中减少量化噪声的方法和装置

    公开(公告)号：US20050094757A1

    公开(公告)日：2005-05-05

    申请号：US10701732

    申请日：2003-11-05

    申请人： Scott Meninger ,  Michael Perrott

    发明人： Scott Meninger ,  Michael Perrott

    IPC分类号： H03D3/24 ,  H03L7/087 ,  H03L7/089 ,  H03L7/197

    CPC分类号： H03L7/1976 ,  H03L7/087 ,  H03L7/0898

    摘要： Described are methods and modules for reducing the phase noise generated in a fractional-N frequency synthesizer. The methods are based on swapping phase signals to achieve the same average delay for each phase signal path, compensation and resynchronization of phase signals and shuffling of digital-to-analog unit elements used to produce specific quantization levels. One method is based on digital gain compensation used to correct for frequency-dependent error arising from differences between horizontal slicing quantization techniques and conventional vertical slicing techniques. Also described are a combined phase detector and DAC module and a method for extending its range.

    摘要翻译： 描述了用于减小分数N频率合成器中产生的相位噪声的方法和模块。 这些方法基于交换相位信号，以实现每个相位信号路径的相同平均延迟，相位信号的补偿和重新同步以及用于产生特定量化电平的数模转换单元的混洗。 一种方法是基于用于校正由水平切片量化技术和常规垂直切片技术之间的差异引起的频率相关误差的数字增益补偿。 还描述了组合相位检测器和DAC模块以及用于扩展其范围的方法。

    Gated ring oscillator for a time-to-digital converter with shaped quantization noise
    6.
    发明授权
    Gated ring oscillator for a time-to-digital converter with shaped quantization noise 有权
    具有成形量化噪声的时间到数字转换器的门控环形振荡器

    公开(公告)号：US08138843B2

    公开(公告)日：2012-03-20

    申请号：US11854615

    申请日：2007-09-13

    申请人： Matthew Straayer ,  Michael Perrott

    发明人： Matthew Straayer ,  Michael Perrott

    IPC分类号： H03K3/03 ,  G01R23/175 ,  G04F10/04

    CPC分类号： H03K3/0315 ,  G04F10/005 ,  H03K23/54

    摘要： Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter includes a plurality of delay stages configured to enable propagation of a transitioning signal through the delay stages during an enabled state and configured to inhibit propagation of the transitioning signal through the delay stages during a disabled state. Delay stages are interconnected to allow sustained transitions to propagate through the delay stages during the enabled state and to preserve a state of the gated ring oscillator time-to-digital converter during the disabled state. The state represents a time resolution that is finer than the delay of at least one of the delay stages. A measurement module determines the number of transitions of the delay stages.

    摘要翻译： 描述了一种紧凑的低功率门控环形振荡器时间数字转换器，其使用数字实现来实现量化噪声的一阶噪声整形。 门控环形振荡器时间 - 数字转换器包括多个延迟级，其被配置为能够在使能状态期间使转换信号经过延迟级的传播，并被配置为在禁用状态期间阻止转换信号经过延迟级的传播。 互连延迟级以允许持续转换在使能状态期间传播通过延迟级，并且在禁用状态期间保持门控环形振荡器时间 - 数字转换器的状态。 该状态表示比至少一个延迟级的延迟更精细的时间分辨率。 测量模块确定延迟级的转换次数。

    GATED RING OSCILLATOR FOR A TIME-TO-DIGITAL CONVERTER WITH SHAPED QUANTIZATION NOISE
    7.
    发明申请
    GATED RING OSCILLATOR FOR A TIME-TO-DIGITAL CONVERTER WITH SHAPED QUANTIZATION NOISE 有权
    用于具有形状定量噪声的时间到数字转换器的门环振荡器

    公开(公告)号：US20080069292A1

    公开(公告)日：2008-03-20

    申请号：US11854615

    申请日：2007-09-13

    申请人： Matthew Straayer ,  Michael Perrott

    发明人： Matthew Straayer ,  Michael Perrott

    IPC分类号： H03K23/54 ,  H03K3/00

    CPC分类号： H03K3/0315 ,  G04F10/005 ,  H03K23/54

    摘要： Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter includes a plurality of delay stages configured to enable propagation of a transitioning signal through the delay stages during an enabled state and configured to inhibit propagation of the transitioning signal through the delay stages during a disabled state. Delay stages are interconnected to allow sustained transitions to propagate through the delay stages during the enabled state and to preserve a state of the gated ring oscillator time-to-digital converter during the disabled state. The state represents a time resolution that is finer than the delay of at least one of the delay stages. A measurement module determines the number of transitions of the delay stages.

    摘要翻译： 描述了一种紧凑的低功率门控环形振荡器时间数字转换器，其使用数字实现来实现量化噪声的一阶噪声整形。 门控环形振荡器时间 - 数字转换器包括多个延迟级，其被配置为能够在使能状态期间使转换信号经过延迟级的传播，并被配置为在禁用状态期间阻止转换信号经过延迟级的传播。 互连延迟级以允许持续转换在使能状态期间传播通过延迟级，并且在禁用状态期间保持门控环形振荡器时间 - 数字转换器的状态。 该状态表示比至少一个延迟级的延迟更精细的时间分辨率。 测量模块确定延迟级的转换次数。

    Method and apparatus for acquiring a frequency without a reference clock
    8.
    发明授权
    Method and apparatus for acquiring a frequency without a reference clock 有权
    用于在没有参考时钟的情况下获取频率的方法和装置

    公开(公告)号：US07205852B2

    公开(公告)日：2007-04-17

    申请号：US11057466

    申请日：2005-02-14

    申请人： Michael Perrott

    发明人： Michael Perrott

    IPC分类号： H03L7/00 ,  H03L7/10

    CPC分类号： H04L1/205 ,  H03L7/085 ,  H03L7/099 ,  H03L7/10 ,  H04L7/033 ,  H04L2027/0016 ,  Y10S331/02

    摘要： A clock and data recovery system acquires a clock embedded in an input data stream by detecting the occurrence of transitions in the input data stream falling into a predetermined phase zone of a sample clock used to sample the input data stream. A control circuit counts how many evaluation intervals have at least one transition in the predetermined phase zone. The control circuit determines if lock is achieved according to the count. If it is determined that lock is not achieved, an output of a variable oscillator circuit used in the clock recovery operation is adjusted until the number of evaluation intervals having one or more transitions in the predetermined phase zone is below a level indicating lock.

    摘要翻译： 时钟和数据恢复系统通过检测落入用于对输入数据流进行采样的采样时钟的预定相位区域的输入数据流中的转变的发生而获取嵌入在输入数据流中的时钟。 控制电路计数多少评估间隔在预定相区中具有至少一个转变。 控制电路根据计数确定是否实现锁定。 如果确定没有实现锁定，则调整在时钟恢复操作中使用的可变振荡器电路的输出，直到在预定相位区域中具有一个或多个转换的评估间隔的数量低于指示锁定的电平。

    Method and apparatus for acquiring a frequency without a reference clock
    9.
    发明申请
    Method and apparatus for acquiring a frequency without a reference clock 有权
    用于在没有参考时钟的情况下获取频率的方法和装置

    公开(公告)号：US20050147197A1

    公开(公告)日：2005-07-07

    申请号：US11057466

    申请日：2005-02-14

    申请人： Michael Perrott

    发明人： Michael Perrott

    IPC分类号： H03D3/24 ,  H03L7/00 ,  H03L7/085 ,  H03L7/099 ,  H03L7/10 ,  H04L1/20 ,  H04L7/033 ,  H04L27/00

    CPC分类号： H04L1/205 ,  H03L7/085 ,  H03L7/099 ,  H03L7/10 ,  H04L7/033 ,  H04L2027/0016 ,  Y10S331/02

    摘要： A clock and data recovery system acquires a clock embedded in an input data stream by detecting the occurrence of transitions in the input data stream falling into a predetermined phase zone of a sample clock used to sample the input data stream. A control circuit counts how many evaluation intervals have at least one transition in the predetermined phase zone. The control circuit determines if lock is achieved according to the count. If it is determined that lock is not achieved, an output of a variable oscillator circuit used in the clock recovery operation is adjusted until the number of evaluation intervals having one or more transitions in the predetermined phase zone is below a level indicating lock.

    摘要翻译： 时钟和数据恢复系统通过检测落入用于对输入数据流进行采样的采样时钟的预定相位区域的输入数据流中的转变的发生而获取嵌入在输入数据流中的时钟。 控制电路计数多少评估间隔在预定相区中具有至少一个转变。 控制电路根据计数确定是否实现锁定。 如果确定没有实现锁定，则调整在时钟恢复操作中使用的可变振荡器电路的输出，直到在预定相位区域中具有一个或多个转换的评估间隔的数量低于指示锁定的电平。