公开(公告)号：US06717874B1

公开(公告)日：2004-04-06

申请号：US10218892

申请日：2002-08-14

申请人： Frederick A. Perner ,  David H. McIntyre ,  Jonathan Jedwab ,  Anthony P. Holden

发明人： Frederick A. Perner ,  David H. McIntyre ,  Jonathan Jedwab ,  Anthony P. Holden

IPC分类号： G11C702

CPC分类号： G11C7/06 ,  G11C7/1006

摘要： Systems and methods for reducing the effect of noise while reading data in series from memory, are provided. One system embodiment comprises a memory cell that stores a first data; a sensing device that receives the first data multiple times and provides a first set of outputs; and a voting system that evaluates the first set of outputs to determine whether one of the outputs of the first set is valid data from the memory cell. One method embodiment comprises reading data in series that is stored in a memory cell to provide outputs; and evaluating the outputs to determine whether one of the outputs is valid data from the memory cell.

摘要翻译： 提供了用于在从存储器中串行读取数据时降低噪声影响的系统和方法。 一个系统实施例包括存储第一数据的存储器单元; 感测装置，其多次接收第一数据并提供第一组输出; 以及投票系统，其评估所述第一组输出以确定所述第一组的输出中的一个是来自所述存储器单元的有效数据。 一种方法实施例包括读取存储在存储单元中以提供输出的串联数据; 以及评估所述输出以确定所述输出中的一个是来自所述存储器单元的有效数据。

公开(公告)号：US07036068B2

公开(公告)日：2006-04-25

申请号：US09915194

申请日：2001-07-25

申请人： James Andrew Davis ,  Jonathan Jedwab ,  David H. McIntyre ,  Kenneth Graham Paterson ,  Frederick A Perner ,  Gadiel Seroussi ,  Kenneth K Smith ,  Stewart R. Wyatt

发明人： James Andrew Davis ,  Jonathan Jedwab ,  David H. McIntyre ,  Kenneth Graham Paterson ,  Frederick A Perner ,  Gadiel Seroussi ,  Kenneth K Smith ,  Stewart R. Wyatt

IPC分类号： G11C29/00

CPC分类号： G06F11/1008

摘要： A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells 16 of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols 206 in a block of ECC encoded data 204 which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells 16. Where the position of suspected failed symbols 206 is known from this erasure information, the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

摘要翻译： 磁阻固态存储装置（MRAM）采用纠错编码（ECC）来形成ECC编码的存储数据。 在读操作中，从设备的存储单元16获得参数值，并与与擦除信息一起建立逻辑位值的范围进行比较。 擦除信息识别ECC编码数据204的块中的符号206，其从参数评估被怀疑受到存储单元16的物理故障的影响。 在从该擦除信息中知道可疑故障符号206的位置的情况下，解码器22执行ECC解码的能力被显着提高。

公开(公告)号：US06678197B1

公开(公告)日：2004-01-13

申请号：US10273623

申请日：2002-10-18

申请人： Frederick A. Perner ,  Kenneth K. Smith ,  David H. McIntyre ,  Sarah M. Brandenberger ,  Terrel R. Munden ,  Robert Sesek

发明人： Frederick A. Perner ,  Kenneth K. Smith ,  David H. McIntyre ,  Sarah M. Brandenberger ,  Terrel R. Munden ,  Robert Sesek

IPC分类号： G11C702

CPC分类号： G11C7/02 ,  G11C7/06 ,  G11C7/1006

摘要： Systems and methods for reducing the effect of noise while reading data from memory, are provided. One system embodiment includes a memory cell that stores a first data; multiple sensing devices that receive the first data and provide a first set of outputs; and a voting system that evaluates the first set of outputs to determine whether one of the outputs of the first set is valid data from the memory cell. One method embodiment includes reading data in parallel that is stored in a memory cell to provide outputs; and evaluating the outputs to determine whether one of the outputs is valid data from the memory cell.

摘要翻译： 提供了用于在从存储器读取数据的同时降低噪声的影响的系统和方法。 一个系统实施例包括存储第一数据的存储单元; 多个感测装置，其接收第一数据并提供第一组输出; 以及投票系统，其评估所述第一组输出以确定所述第一组的输出中的一个是来自所述存储器单元的有效数据。 一种方法实施例包括并行读取存储在存储单元中以提供输出的数据; 以及评估所述输出以确定所述输出中的一个是来自所述存储器单元的有效数据。

公开(公告)号：US5610506A

公开(公告)日：1997-03-11

申请号：US559034

申请日：1995-11-15

申请人： David H. McIntyre

发明人： David H. McIntyre

IPC分类号： G01R17/00 ,  G01R1/28 ,  G01R19/165 ,  G05F1/56 ,  G05F3/24 ,  G11C16/06 ,  G11C17/00 ,  G05F3/16

CPC分类号： G05F3/247

摘要： A reference circuit is provided which generates a reference voltage which is always at least as high as a stable reference value. This is done by generating a lock signal which is maintained at a first logic level during start-up of the reference circuit and then attains a second logic level when the reference value has stabilized. The reference circuit can be a bandgap reference circuit.

摘要翻译： 提供了一种参考电路，其产生始终至少与稳定参考值一样高的参考电压。 这通过产生锁定信号来完成，锁定信号在参考电路启动期间保持在第一逻辑电平，然后当参考值稳定时达到第二逻辑电平。 参考电路可以是带隙参考电路。

公开(公告)号：US5757814A

公开(公告)日：1998-05-26

申请号：US519406

申请日：1995-08-24

申请人： David H. McIntyre

发明人： David H. McIntyre

IPC分类号： G01R31/28 ,  G11C16/06 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  G06F11/00

CPC分类号： G11C29/24 ,  G11C29/04 ,  G11C29/78

摘要： A redundancy implementation circuit has a set of memory cells each storing an address bit of an address identifying a redundant memory location and a set of comparator circuits each connected to compare the address bit stored in a memory cell with an incoming address bit. A switch selectively connects the output of the memory cell to a redundant address line supplying the incoming address bit during a test mode. A redundant address line driver is activated for supplying an incoming address bit onto the redundant address line in a normal mode, and a test line output driver is connected to the redundant address line in a test mode for utilising the redundant address line to supply test signals onto a test path.

摘要翻译： 冗余实现电路具有一组存储器单元，每个存储器单元存储标识冗余存储器位置的地址的地址位和一组比较器电路，每个比较器电路连接以将存储在存储器单元中的地址位与输入地址位进行比较。 在测试模式期间，开关选择性地将存储器单元的输出连接到提供输入地址位的冗余地址线。 激活冗余地址线驱动器，以正常模式将输入地址位提供给冗余地址线，测试线输出驱动器以测试模式连接到冗余地址线，以利用冗余地址线提供测试信号 到测试路径。

公开(公告)号：US07467264B2

公开(公告)日：2008-12-16

申请号：US10607624

申请日：2003-06-27

申请人： Richard L. Hilton ,  Anthony Holden ,  Steven C. Johnson ,  David H. McIntyre ,  Kenneth K. Smith

发明人： Richard L. Hilton ,  Anthony Holden ,  Steven C. Johnson ,  David H. McIntyre ,  Kenneth K. Smith

IPC分类号： G06F12/00 ,  G11C11/00 ,  H03M13/41

CPC分类号： G11C8/10

摘要： Methods and apparatuses are disclosed for measuring values of a plurality of memory elements, where the measured values may be indicative of the digital state of a memory element. Calculations may be performed on a plurality of transition-terms associated with the possible transitions in the values between proximate memory elements. The digital state of memory elements may be determined using the calculations performed on the plurality of transition-terms.

摘要翻译： 公开了用于测量多个存储元件的值的方法和装置，其中测量值可以指示存储元件的数字状态。 可以对与相邻存储器元件之间的值中的可能转换相关联的多个转换项执行计算。 存储器元件的数字状态可以使用对多个转换项执行的计算来确定。

公开(公告)号：US06809958B2

公开(公告)日：2004-10-26

申请号：US10243469

申请日：2002-09-13

申请人： Darrel Bloomquist ,  David H. McIntyre

发明人： Darrel Bloomquist ,  David H. McIntyre

IPC分类号： G11C1115

CPC分类号： G11C11/15

摘要： A magnetic random access memory array includes a data storage layer having an easy axis. A non-linear first conductor is positioned on a first side of the data storage layer, wherein a portion of the first conductor has an angle of orientation that is perpendicular to the easy axis. A non-linear second conductor is positioned on a second side of the data storage layer, wherein a portion of the second conductor also has an angle of orientation that is perpendicular to the easy axis.

公开(公告)号：US5629611A

公开(公告)日：1997-05-13

申请号：US519341

申请日：1995-08-24

申请人： David H. McIntyre

发明人： David H. McIntyre

IPC分类号： G11C17/00 ,  G05F3/26 ,  G05F3/30 ,  G11C5/14 ,  G11C16/06 ,  G05F3/16

CPC分类号： G11C5/147 ,  G05F3/267 ,  G05F3/30

摘要： A current generator provides a substantially constant current. The current generator is based on a bandgap circuit and additionally include a current setting device which is located to receive the output signal of the operational amplifier of the bandgap circuit and which is arranged to provide a substantially constant reference current. The circuit is used to particular advantage in a flash memory device.

摘要翻译： 电流发生器提供基本恒定的电流。 电流发生器基于带隙电路，并且还包括电流设置装置，其被定位为接收带隙电路的运算放大器的输出信号，并且被布置为提供基本恒定的参考电流。 该电路在闪速存储器件中特别有利。

公开(公告)号：US5619449A

公开(公告)日：1997-04-08

申请号：US559695

申请日：1995-11-15

申请人： David H. McIntyre

发明人： David H. McIntyre

IPC分类号： G11C17/00 ,  G11C7/14 ,  G11C11/401 ,  G11C11/4099 ,  G11C16/06 ,  G11C16/28 ,  G11C16/04

CPC分类号： G11C16/28 ,  G11C11/4099 ,  G11C7/14

摘要： A memory comprises first and second arrays of memory cells organised in rows and column. The cells in each row are connected to respective wordlines and the cells in each column are connected to a respective bit line. Wordlines of the first array are addressable independently of the wordlines of the second array. A sense amplifier is provided to sense the differential between a signal on the bit line of a selected cell in one array and a reference signal. A current souce is selectively connectable to supply the reference signal for comparison with the signal on the bit line of the addressed array. The present invention allows capacitive balancing to be achieved without the need for dummy cells.

摘要翻译： 存储器包括以行和列组织的第一和第二存储器单元阵列。 每行中的单元连接到相应的字线，并且每列中的单元连接到相应的位线。 第一个阵列的字词可以独立于第二个数组的字线寻址。 提供读出放大器以感测一个阵列中所选择的单元的位线上的信号与参考信号之间的差分。 可选择性地连接电流源以提供参考信号以与寻址的阵列的位线上的信号进行比较。 本发明允许在不需要虚设单元的情况下实现电容平衡。