公开(公告)号：US09607953B1

公开(公告)日：2017-03-28

申请号：US15052229

申请日：2016-02-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Lu Li ,  Hamdan Ismail ,  Samy R. N. Naidu ,  Mahesh Shah

IPC: H01L27/00 ,  H01L23/66 ,  H01L23/31 ,  H01L25/18 ,  H01L25/065 ,  H01L29/49 ,  H01L23/552 ,  H01L21/56 ,  H01L25/00 ,  H03F3/21 ,  H03F1/26 ,  H03F1/02

CPC classification number: H01L23/66 ,  H01L21/56 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/552 ,  H01L25/0655 ,  H01L29/49 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/141 ,  H01L2924/181 ,  H01L2924/3025 ,  H03F1/0288 ,  H03F3/195 ,  H03F2200/451 ,  H01L2224/45099

Abstract: A semiconductor device package includes an isolation wall located between a first circuit and a second circuit on a substrate. The isolation wall is configured to reduce inductive coupling between the first and second circuits during operation of the semiconductor device. Encapsulation material covers the substrate, first and second circuits, and the isolation wall. The isolation wall has features, such as indentation, along its upper edge that facilitate a flow of the encapsulation material across the isolation wall during fabrication to largely eliminate interior defects and/or visual defects on the surface of the completed semiconductor device package. For a dual-path amplifier, such as a Doherty power amplifier, the isolation wall separates the carrier amplifier elements from the peaking amplifier elements included within the semiconductor device package.

公开(公告)号：US20150235933A1

公开(公告)日：2015-08-20

申请号：US14184266

申请日：2014-02-19

Applicant: Freescale Semiconductor, Inc.

Inventor： Hussain H. Ladhani ,  Lu Li ,  Mahesh K. Shah ,  Lakshminarayan Viswanathan ,  Michael E. Watts

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H03F3/193 ,  H03F3/21

CPC classification number: H01L21/4853 ,  H01L23/66 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F3/21 ,  H03F2200/423 ,  H03F2200/451 ,  H01L2924/00014

Abstract: A semiconductor device, related package, and method of manufacturing same are disclosed. In at least one embodiment, the semiconductor device includes a radio frequency (RF) power amplifier transistor having a first port, a second port, and a third port. The semiconductor device also includes an output lead, a first output impedance matching circuit between the second port and the output lead, and a first additional circuit coupled between the output lead and a ground terminal. At least one component of the first additional circuit is formed at least in part by way of one or more of a plurality of castellations and a plurality of vias.

Abstract translation: 公开了一种半导体器件，相关封装及其制造方法。 在至少一个实施例中，半导体器件包括具有第一端口，第二端口和第三端口的射频（RF）功率放大器晶体管。 半导体器件还包括输出引线，第二端口和输出引线之间的第一输出阻抗匹配电路，以及耦合在输出引线和接地端子之间的第一附加电路。 第一附加电路的至少一个部件至少部分地通过多个城堡和多个通孔中的一个或多个形成。

公开(公告)号：US09484222B2

公开(公告)日：2016-11-01

申请号：US14184266

申请日：2014-02-19

Applicant: Freescale Semiconductor, Inc.

Inventor： Hussain H. Ladhani ,  Lu Li ,  Mahesh K. Shah ,  Lakshminarayan Viswanathan ,  Michael E. Watts

IPC: H01L23/02 ,  H01L27/08 ,  H01L21/48 ,  H03F3/193 ,  H03F3/21 ,  H01L25/00 ,  H01L23/66 ,  H03F1/56 ,  H03F3/195

CPC classification number: H01L21/4853 ,  H01L23/66 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F3/21 ,  H03F2200/423 ,  H03F2200/451 ,  H01L2924/00014

Abstract: A semiconductor device, related package, and method of manufacturing same are disclosed. In at least one embodiment, the semiconductor device includes a radio frequency (RF) power amplifier transistor having a first port, a second port, and a third port. The semiconductor device also includes an output lead, a first output impedance matching circuit between the second port and the output lead, and a first additional circuit coupled between the output lead and a ground terminal. At least one component of the first additional circuit is formed at least in part by way of one or more of a plurality of castellations and a plurality of vias.

Abstract translation: 公开了一种半导体器件，相关封装及其制造方法。 在至少一个实施例中，半导体器件包括具有第一端口，第二端口和第三端口的射频（RF）功率放大器晶体管。 半导体器件还包括输出引线，第二端口和输出引线之间的第一输出阻抗匹配电路，以及耦合在输出引线和接地端子之间的第一附加电路。 第一附加电路的至少一个部件至少部分地通过多个城堡和多个通孔中的一个或多个形成。