公开(公告)号：US07067917B2

公开(公告)日：2006-06-27

申请号：US10337292

申请日：2003-01-07

申请人： Fu-Tai Liou ,  Cheng-Yu Hung ,  Tri-Rung Yew

发明人： Fu-Tai Liou ,  Cheng-Yu Hung ,  Tri-Rung Yew

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76846 ,  C23C14/027 ,  C23C14/0641 ,  C23C16/029 ,  C23C16/34 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76805 ,  H01L21/76864 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/26 ,  H01L2924/00

摘要： The present invention is directed to a structure of a gradient barrier layer. The gradient barrier with a composite structure of metal/metal salt of different composition/metal such as Ta/TaxN1−x/TaN/TaxN1−x/Ta (tantalum/tantalumx nitride1−x/tantalum nitride/tantalumx nitride1−x/tantalum) is proposed to replace the conventional barrier for copper metallization. The gradient barrier can be formed in a chemical vapor deposition (CVD) process or a multi-target physical vapor deposition (PVD) process. For CVD process, using the characteristics of well-controlled reaction gas injection, the ratio of tantalum (Ta) and nitrogen (N) can be modulated gradually to form the gradient barrier. For the multi-target PVD process, the gradient barrier is formed by depositing multi-layers of different composition TaxN1−x films. After subsequent thermal cycle processes such as metal alloy, the inter-layer diffusion occurs and a more smooth distribution of Ta and N is achieved for the gradient barrier. The advantages of forming the gradient barrier include a well-controlled process, a strong adhesion between via and landing metal, more uniform step coverage, and less brittle to reduce crack.

摘要翻译： 本发明涉及梯度阻挡层的结构。 具有不同成分/金属的金属/金属盐的复合结构的梯度屏障，例如Ta / Ta x N 1-x / TaN / Ta x x 1 / x 1 / x 3/1 / x 2/1 / x 3 / 提出了替代传统的铜金属化屏障的方法。 梯度屏障可以在化学气相沉积（CVD）工艺或多目标物理气相沉积（PVD）工艺中形成。 对于CVD工艺，使用良好控制的反应气体注入特性，可以逐渐调节钽（Ta）和氮（N）的比例，形成梯度屏障。 对于多目标PVD工艺，通过沉积多层不同组成的Ta x N 1 x-x膜形成梯度屏障。 在随后的热循环过程如金属合金之后，发生层间扩散，并且对梯度屏障实现了更平稳的Ta和N分布。 形成梯度屏障的优点包括良好控制的工艺，通孔和着陆金属之间的牢固粘附，更均匀的台阶覆盖，并且较不易碎以减少裂纹。

公开(公告)号：US06287963B1

公开(公告)日：2001-09-11

申请号：US08418257

申请日：1995-04-06

申请人： Fusen E. Chen ,  Fu-Tai Liou ,  Girish A. Dixit ,  Che-Chia Wei

发明人： Fusen E. Chen ,  Fu-Tai Liou ,  Girish A. Dixit ,  Che-Chia Wei

IPC分类号： H01L214763

CPC分类号： H01L23/53223 ,  C23C16/0281 ,  C23C16/20 ,  H01L21/28512 ,  H01L21/32051 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The deposition step is periodically interrupted.

摘要翻译： 提供了一种用于在半导体集成电路器件中沉积铝薄膜层以形成接触的方法。 所有或一些沉积过程在允许沉积的铝原子的表面迁移的温度下以相对低的沉积速率发生。 在这些条件下沉积的铝倾向于填充接触孔而不形成空隙。 沉积步骤被周期性地中断。

公开(公告)号：US06271137B1

公开(公告)日：2001-08-07

申请号：US08146823

申请日：1993-11-01

申请人： Fu-Tai Liou ,  Fusen E. Chen

发明人： Fu-Tai Liou ,  Fusen E. Chen

IPC分类号： H01L2144

CPC分类号： H01L23/53223 ,  C23C16/0281 ,  C23C16/20 ,  H01L21/28512 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming improved quality interlevel aluminum contacts in semiconductor integrated circuits. A contact opening is formed through an insulating layer. A barrier layer is deposited over the surface of the integrated circuit. An aluminum layer is then deposited at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

摘要翻译： 提供了一种用于在半导体集成电路中形成改进的质量层间铝触点的方法。 通过绝缘层形成接触开口。 势垒层沉积在集成电路的表面上。 然后在允许改善沉积的铝原子的表面迁移的温度下以相对低的沉积速率沉积铝层。 在这些条件下沉积的铝倾向于填充接触孔而不形成空隙。 低温沉积步骤可以通过沉积铝来开始，而包含集成电路器件的晶片正在从沉积室内的较冷的温度加热。

公开(公告)号：US6111319A

公开(公告)日：2000-08-29

申请号：US575691

申请日：1995-12-19

申请人： Fu-Tai Liou ,  Mehdi Zamanian

发明人： Fu-Tai Liou ,  Mehdi Zamanian

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48

CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76807

摘要： A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening. According to a further alternate embodiment, an etch stop layer is formed between the insulating layer and conductive region and an opening is formed in the insulating layer exposing the etch stop layer. A sidewall spacer film is formed over the insulating layer and the etch stop layer, both layers having a similar etch rate for a given etchant. The etch stop and spacer layers are etched in the opening to expose the underlying conductive layer thereby forming a contiguous sidewall spacer and etch stop layer on the sides of and under the insulating layer, thereby decreasing the contact dimension of the opening.

摘要翻译： 公开了一种通过半导体集成电路或接触形成小几何形状的方法，以及根据该半导体集成电路形成的集成电路。 根据第一公开的实施例，部分地通过覆盖导电区域的绝缘层形成开口。 沿着开口的侧壁形成侧壁间隔物。 蚀刻剩余的绝缘层以暴露下面的导电区域。 开口的接触尺寸小于可以用现代光刻技术印刷的开口。 根据替代实施例，绝缘层中的开口暴露下面的导电区域。 在绝缘层和开口中形成多晶硅层。 多晶硅被氧化以在开口中形成厚的氧化物并被回蚀以形成减小开口的接触尺寸的氧化的多晶硅侧壁间隔物。 根据另一替代实施例，在绝缘层和导电区域之间形成蚀刻停止层，并且在暴露蚀刻停止层的绝缘层中形成开口。 在绝缘层和蚀刻停止层上形成侧壁间隔膜，两层对于给定的蚀刻剂具有相似的蚀刻速率。 蚀刻停止层和间隔层在开口中被蚀刻以暴露下面的导电层，从而在绝缘层上和下方形成连续的侧壁间隔物和蚀刻停止层，从而减小开口的接触尺寸。

公开(公告)号：US5847460A

公开(公告)日：1998-12-08

申请号：US574659

申请日：1995-12-19

申请人： Fu-Tai Liou ,  Mehdi Zamanian

发明人： Fu-Tai Liou ,  Mehdi Zamanian

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/52 ,  H01L23/58 ,  H01L29/40

CPC分类号： H01L21/76831 ,  H01L21/76807

摘要： A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening. According to a further alternate embodiment, an etch stop layer is formed between the insulating layer and conductive region and an opening is formed in the insulating layer exposing the etch stop layer. A sidewall spacer film is formed over the insulating layer and the etch stop layer, both layers having a similar etch rate for a given etchant. The etch stop and spacer layers are etched in the opening to expose the underlying conductive layer thereby forming a contiguous sidewall spacer and etch stop layer on the sides of and under the insulating layer, thereby decreasing the contact dimension of the opening.

摘要翻译： 公开了一种通过半导体集成电路或接触形成小几何形状的方法，以及根据该半导体集成电路形成的集成电路。 根据第一公开的实施例，部分地通过覆盖导电区域的绝缘层形成开口。 沿着开口的侧壁形成侧壁间隔物。 蚀刻剩余的绝缘层以暴露下面的导电区域。 开口的接触尺寸小于可以用现代光刻技术印刷的开口。 根据替代实施例，绝缘层中的开口暴露下面的导电区域。 在绝缘层和开口中形成多晶硅层。 多晶硅被氧化以在开口中形成厚的氧化物并被回蚀以形成减小开口的接触尺寸的氧化的多晶硅侧壁间隔物。 根据另一替代实施例，在绝缘层和导电区域之间形成蚀刻停止层，并且在暴露蚀刻停止层的绝缘层中形成开口。 在绝缘层和蚀刻停止层上形成侧壁间隔膜，两层对于给定的蚀刻剂具有相似的蚀刻速率。 蚀刻停止层和间隔层在开口中被蚀刻以暴露下面的导电层，从而在绝缘层上和下方形成连续的侧壁间隔物和蚀刻停止层，从而减小开口的接触尺寸。

公开(公告)号：US5462894A

公开(公告)日：1995-10-31

申请号：US310925

申请日：1994-09-22

申请人： Charles R. Spinner ,  Fu-Tai Liou

发明人： Charles R. Spinner ,  Fu-Tai Liou

IPC分类号： H01L21/02 ,  H01L27/11 ,  H01L29/8605

CPC分类号： H01L28/20 ,  H01L27/1112 ,  Y10S148/136 ,  Y10S257/904

摘要： A method for forming integrated circuit structures includes the formation of high-value resistive elements and low resistance interconnect in a single polycrystalline layer. In one embodiment, interconnect regions of the polycrystalline silicon layer are masked, and resistive element regions are partially oxidized to reduce the thickness of the polycrystalline layer in such regions. Resistivity of the interconnect regions may then be reduced by implanting a high level of impurities in them, or by forming a refractory metal silicide layer over the interconnect regions. The oxide formed over the resistive elements during the oxidation thereof protects them from either of the following process steps, so that no masking is required. In an alternative embodiment, silicidation of the interconnect regions of the polycrystalline silicon layer may be performed without the prior local oxidations of the resistive element regions.

摘要翻译： 一种用于形成集成电路结构的方法包括在单个多晶层中形成高价值电阻元件和低电阻互连。 在一个实施例中，多晶硅层的互连区域被掩蔽，并且电阻元件区域被部分氧化以减小这些区域中的多晶层的厚度。 然后可以通过在其中注入高水平的杂质或通过在互连区域上形成难熔金属硅化物层来减小互连区域的电阻率。 在氧化过程中在电阻元件上形成的氧化物保护它们免于以下任一工艺步骤，从而不需要掩蔽。 在替代实施例中，多晶硅层的互连区域的硅化可以在电阻元件区域的先前局部氧化的情况下进行。

公开(公告)号：US5270254A

公开(公告)日：1993-12-14

申请号：US676084

申请日：1991-03-27

申请人： Fusen E. Chen ,  Fu-Tai Liou

发明人： Fusen E. Chen ,  Fu-Tai Liou

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L21/76847 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/97

摘要： A method for forming aluminum metallization for contacting a conductive element in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, a first aluminum alloy layer is formed within the contact, optionally with a barrier layer between it and the underlying electrode. An etch stop layer is formed thereover, of a material which has a low etch rate to an aluminum etchant species. A second, thicker, aluminum alloy layer is formed thereover. The second aluminum layer is etched until the etch stop layer is reached; the mask for defining the metal line may have an edge within the dimensions of the contact opening. After removal of the exposed etch stop layer, a timed etch removes the first aluminum alloy layer, without exposing the bottom of the contact. The metal line may thus be safely formed, without requiring an enclosure around the contact opening. According to an alternate embodiment, conductive or semiconductive sidewall spacers may be formed, upon which the metal etch can stop, leaving a metal line within the contact dimensions. A further alternative embodiment uses a conductive etch stop layer which covers the entire contact, and upon which the metal etch can stop within the contact opening.

公开(公告)号：US5268325A

公开(公告)日：1993-12-07

申请号：US741793

申请日：1991-08-06

申请人： Charles R. Spinner, III ,  Fu-Tai Liou

发明人： Charles R. Spinner, III ,  Fu-Tai Liou

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H01L27/11 ,  H01L21/70

CPC分类号： H01L28/20 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53271 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S148/136

摘要： A method for forming integrated circuit structures includes the formation of high-value resistive elements and low resistance interconnect in a single polycrystalline layer. In one embodiment, interconnect regions of the polycrystalline silicon layer are masked, and resistive element regions are partially oxidized to reduce the thickness of the polycrystalline layer in such regions. Resistivity of the interconnect regions may then be reduced by implanting a high level of impurities in them, or by forming a refractory metal silicide layer over the interconnect regions. The oxide formed over the resistive elements during the oxidation thereof protects them from either of the following process steps, so that no masking is required. In an alternative embodiment, silicidation of the interconnect regions of the polycrystalline silicon layer may be performed without the prior local oxidations of the resistive element regions.

摘要翻译： 一种用于形成集成电路结构的方法包括在单个多晶层中形成高价值电阻元件和低电阻互连。 在一个实施例中，多晶硅层的互连区域被掩蔽，并且电阻元件区域被部分氧化以减小这些区域中的多晶层的厚度。 然后可以通过在其中注入高水平的杂质或通过在互连区域上形成难熔金属硅化物层来减小互连区域的电阻率。 在氧化过程中在电阻元件上形成的氧化物保护它们免于以下任一工艺步骤，从而不需要掩蔽。 在替代实施例中，多晶硅层的互连区域的硅化可以在电阻元件区域的先前局部氧化的情况下进行。

公开(公告)号：US5124280A

公开(公告)日：1992-06-23

申请号：US648554

申请日：1991-01-31

申请人： Che-Chia Wei ,  Fu-Tai Liou

发明人： Che-Chia Wei ,  Fu-Tai Liou

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53271 ,  H01L21/76889 ,  H01L21/76895 ,  H01L2924/0002

摘要： Local interconnect is defined in a polycrystalline silicon layer. Openings to underlying conducting regions are made through an insulating layer after the local interconnect conductor definition. A thin extra polycrystalline silicon layer is then deposited over the device and etched back to form polycrystalline silicon sidewall elements. These sidewalls connect the polycrystalline silicon local interconnect conductors to the underlying conductive regions. Standard silicidation techniques are then used to form a refractory metal silicide on the exposed underlying conductive regions, the polycrystalline silicon sidewall elements, and the polycrystalline silicon local interconnect conductors. This results in a complete silicided connection between features connected by the local interconnect conductors.

公开(公告)号：US08988073B2

公开(公告)日：2015-03-24

申请号：US13089410

申请日：2011-04-19

申请人： Nai-Chung Fu ,  Fu-Tai Liou

发明人： Nai-Chung Fu ,  Fu-Tai Liou

IPC分类号： G01R33/02 ,  G01R33/06 ,  G01R33/09

CPC分类号： G01R33/093

摘要： A magnetoresistive sensor is provided. Specifically, multiple layers of or single layer of conductor line are formed at the same level as an insulating layer on a substrate as a bottom conductive layer. A magnetoresistive structure is formed on the bottom conductive layer and has opposite first surface and second surface. The second surface faces toward the substrate and is contacted with the bottom conductive layer. Afterward, another insulating layer is formed on the first surface, a slot is formed at the same level as the another insulating layer and a conductor line is formed in the slot and contacted with the first surface, so that one layer or multiple layers of conductor line can be formed as a top conductive layer. A lengthwise extending direction of each of the bottom and top conductor layers is intersected a lengthwise extending direction of the magnetoresistive structure with an angle.

摘要翻译： 提供了一种磁阻传感器。 具体地，作为底部导电层，在与基板上的绝缘层相同的层上形成多层或单层导体线。 磁阻结构形成在底部导电层上并具有相对的第一表面和第二表面。 第二表面朝向衬底并与底部导电层接触。 之后，在第一表面上形成另一个绝缘层，在另一个绝缘层上形成一个相同电平的槽，并且在槽中形成导体线并与第一表面接触，使得一层或多层导体 线可以形成为顶部导电层。 每个底部和顶部导体层的纵向延伸方向以一个角度与磁阻结构的纵向延伸方向相交。