公开(公告)号：US10248180B2

公开(公告)日：2019-04-02

申请号：US14704240

申请日：2015-05-05

Applicant: Futurewei Technologies, Inc.

Inventor： Wei Chen ,  Tongzeng Yang ,  Konggang Wei

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3293

Abstract: A processing system includes multiple processors in which a first processor operates at a first clock frequency and first supply voltage at all times. At least one processor is dynamically switchable to operate at the first clock frequency and first supply voltage resulting in the first and second processors providing symmetrical multi-processing (SMP) or at a second clock frequency and a second supply voltage resulting in the first and second processors providing asymmetrical multi-processing (ASMP). An integrated controller (e.g., finite state-machine (FSM)) controls not only voltage change, but also clock-switching. Various criteria can be used to determine when to switch the at least one switchable processor to improve power consumption and/or performance. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control a voltage supply and CPU/memory clock to the switchable processor and cache memory.

公开(公告)号：US09608605B2

公开(公告)日：2017-03-28

申请号：US14820380

申请日：2015-08-06

Applicant: Futurewei Technologies, Inc.

Inventor： Wei Chen ,  Tongzeng Yang ,  Chukwuchebem Chinemelum Orakwue

IPC: H03K5/00 ,  H03K5/003 ,  H03K3/03 ,  H03K5/26

CPC classification number: H03K5/003 ,  G05F1/10 ,  G06F1/26 ,  G06F1/28 ,  H03K3/0315 ,  H03K5/26 ,  H03K19/00369

Abstract: A method and apparatus for measuring a voltage are disclosed. In an embodiment a method for controlling a supply voltage includes providing a first periodic signal by providing a reference voltage to an oscillator, providing a second periodic signal by providing the supply voltage (VOUT) of a voltage source to the oscillator, providing a first count by measuring first periods of the first periodic signal, providing a second count by measuring second periods of the second periodic signal and comparing the first count with the second count.

公开(公告)号：US20170024000A1

公开(公告)日：2017-01-26

申请号：US14806547

申请日：2015-07-22

Applicant: Futurewei Technologies, Inc.

Inventor： Wei Chen ,  Tongzeng Yang

IPC: G06F1/32

CPC classification number: G06F1/3293 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/46 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

Abstract: The present disclosure describes methods, systems, and computer program products for a multiple-processor system. The multiple-processor system includes a plurality of central processing unit (CPU) cores. Each of the plurality of CPU cores is configured to operate in at least one of a plurality of CPU states. The plurality of CPU states includes a low-voltage memory retention (NAP) state, an active state, and a shut-off state. The NAP state includes a sleep state that retains state memory. The multiple-processor system also includes a voltage regulator that is configured to provide a NAP voltage to the plurality of CPU cores. The NAP voltage is sufficient for at least one of the plurality of CPU cores to retain state information and the NAP voltage is lower than an active state voltage. The multiple-processor system further includes a plurality of state control switches. Each of the plurality of state control switches connects the voltage regulator to one of the plurality of CPU cores.

Abstract translation: 本公开描述了用于多处理器系统的方法，系统和计算机程序产品。 多处理器系统包括多个中央处理单元（CPU）核。 多个CPU核心中的每一个被配置为在多个CPU状态中的至少一个中操作。 多个CPU状态包括低电压存储器保持（NAP）状态，激活状态和关闭状态。 NAP状态包括保持状态存储器的休眠状态。 多处理器系统还包括被配置为向多个CPU核提供NAP电压的电压调节器。 NAP电压足以使多个CPU核中的至少一个保持状态信息，并且NAP电压低于有效状态电压。 多处理器系统还包括多个状态控制开关。 多个状态控制开关中的每一个将电压调节器连接到多个CPU核心中的一个。

公开(公告)号：US20180285290A1

公开(公告)日：2018-10-04

申请号：US15942065

申请日：2018-03-30

Applicant: Futurewei Technologies, Inc.

Inventor： Hao Luan ,  Alan Gatherer ,  Xi Chen ,  Fang Yu ,  Yichuan Yu ,  Bin Yang ,  Wei Chen

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A distributed and shared memory controller (DSMC) comprises at least one building block. comprising a plurality of switches distributed into a plurality of stages; a plurality of master ports coupled to a first stage of the switches; and a plurality of bank controllers with associated memory banks coupled to a last stage of the switches; wherein each of the switches connects to lower stage switches via internal connections, each of the switches of the first stage connects to at least one of the master ports via master connections and each of the switches of the last stage connects to at least one of the bank controllers via memory connections; wherein each of the switches of the first stage connects to second stage switches of a neighboring building block via outward connections and each of the switches of a second stage connects to first stage switches of the neighboring building block via inward connections.

公开(公告)号：US09952650B2

公开(公告)日：2018-04-24

申请号：US14516314

申请日：2014-10-16

Applicant: Futurewei Technologies Inc.

Inventor： Wei Chen ,  Tongzeng Yang ,  Anthony Mazzola

IPC: G06F1/32 ,  G06F1/10 ,  G06F9/46

CPC classification number: G06F1/324 ,  G06F1/10 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/46 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: A processing system with multiple processors is switchable between two modes of operation dynamically: symmetrical multi-processing (SMP) and asymmetrical multi-processing (ASMP). The system uses certain criteria to determine when to switch to improve the power consumption or performance. A controller enables control and fast-switching between the two modes. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control voltage supplies and CPU/memory clocks to the multiple processors and cache memory.

公开(公告)号：US20160109923A1

公开(公告)日：2016-04-21

申请号：US14704240

申请日：2015-05-05

Applicant: Futurewei Technologies, Inc.

Inventor： Wei Chen ,  Tongzeng Yang ,  Konggang Wei

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

Abstract: A processing system includes multiple processors in which a first processor operates at a first clock frequency and first supply voltage at all times. At least one processor is dynamically switchable to operate at the first clock frequency and first supply voltage resulting in the first and second processors providing symmetrical multi-processing (SMP) or at a second clock frequency and a second supply voltage resulting in the first and second processors providing asymmetrical multi-processing (ASMP). An integrated controller (e.g., finite state-machine (FSM)) controls not only voltage change, but also clock-switching. Various criteria can be used to determine when to switch the at least one switchable processor to improve power consumption and/or performance. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control a voltage supply and CPU/memory clock to the switchable processor and cache memory.

Abstract translation: 处理系统包括多个处理器，其中第一处理器始终以第一时钟频率和第一电源电压工作。 至少一个处理器可动态切换以在第一时钟频率和第一电源电压下工作，从而导致第一和第二处理器提供对称多处理（SMP）或第二时钟频率和第二电源电压，从而产生第一和第二 提供不对称多处理（ASMP）的处理器。 集成控制器（例如，有限状态机（FSM））不仅控制电压变化，而且控制时钟切换。 可以使用各种标准来确定何时切换至少一个可切换处理器以提高功耗和/或性能。 在接收到切换命令以在SMP和ASMP之间切换时，执行一系列或一系列动作以控制到可切换处理器和高速缓冲存储器的电压供应和CPU /存储器时钟。

公开(公告)号：US10948969B2

公开(公告)日：2021-03-16

申请号：US16371954

申请日：2019-04-01

Applicant: Futurewei Technologies, Inc.

Inventor： Wei Chen ,  Tongzeng Yang ,  Konggang Wei

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3293 ,  G06F1/3287

Abstract: A processing system includes multiple processors in which a first processor operates at a first clock frequency and first supply voltage at all times. At least one processor is dynamically switchable to operate at the first clock frequency and first supply voltage resulting in the first and second processors providing symmetrical multi-processing (SMP) or at a second clock frequency and a second supply voltage resulting in the first and second processors providing asymmetrical multi-processing (ASMP). An integrated controller (e.g., finite state-machine (FSM) controls not only voltage change, but also clock-switching. Various criteria can be used to determine when to switch the at least one switchable processor to improve power consumption and/or performance. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control a voltage supply and CPU/memory clock to the switchable processor and cache memory.

公开(公告)号：US10769080B2

公开(公告)日：2020-09-08

申请号：US15942065

申请日：2018-03-30

Applicant: Futurewei Technologies, Inc.

Inventor： Hao Luan ,  Alan Gatherer ,  Xi Chen ,  Fang Yu ,  Yichuan Yu ,  Bin Yang ,  Wei Chen

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A distributed and shared memory controller (DSMC) comprises at least one building block. comprising a plurality of switches distributed into a plurality of stages; a plurality of master ports coupled to a first stage of the switches; and a plurality of bank controllers with associated memory banks coupled to a last stage of the switches; wherein each of the switches connects to lower stage switches via internal connections, each of the switches of the first stage connects to at least one of the master ports via master connections and each of the switches of the last stage connects to at least one of the bank controllers via memory connections; wherein each of the switches of the first stage connects to second stage switches of a neighboring building block via outward connections and each of the switches of a second stage connects to first stage switches of the neighboring building block via inward connections.

公开(公告)号：US20170040985A1

公开(公告)日：2017-02-09

申请号：US14820380

申请日：2015-08-06

Applicant: Futurewei Technologies, Inc.

Inventor： Wei Chen ,  Tongzeng Yang ,  Chukwuchebem Chinemelum Orakwue

IPC: H03K5/003 ,  H03K5/26 ,  H03K3/03

CPC classification number: H03K5/003 ,  G05F1/10 ,  G06F1/26 ,  G06F1/28 ,  H03K3/0315 ,  H03K5/26 ,  H03K19/00369

Abstract: A method and apparatus for measuring a voltage are disclosed. In an embodiment a method for controlling a supply voltage includes providing a first periodic signal by providing a reference voltage to an oscillator, providing a second periodic signal by providing the supply voltage (VOUT) of a voltage source to the oscillator, providing a first count by measuring first periods of the first periodic signal, providing a second count by measuring second periods of the second periodic signal and comparing the first count with the second count.

Abstract translation: 公开了一种用于测量电压的方法和装置。 在一个实施例中，用于控制电源电压的方法包括通过向振荡器提供参考电压来提供第一周期性信号，通过向振荡器提供电压源的电源电压（VOUT）来提供第二周期性信号，提供第一计数 通过测量第一周期信号的第一周期，通过测量第二周期信号的第二周期并将第一计数与第二计数进行比较来提供第二计数。

公开(公告)号：US20160109921A1

公开(公告)日：2016-04-21

申请号：US14516314

申请日：2014-10-16

Applicant: Futurewei Technologies Inc.

Inventor： Wei Chen ,  Tongzeng Yang ,  Anthony Mazzola

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/10 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/46 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: A processing system with multiple processors is switchable between two modes of operation dynamically: symmetrical multi-processing (SMP) and asymmetrical multi-processing (ASMP). The system uses certain criteria to determine when to switch to improve the power consumption or performance. A controller enables control and fast-switching between the two modes. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control voltage supplies and CPU/memory clocks to the multiple processors and cache memory.

Abstract translation: 具有多个处理器的处理系统可以在两种操作模式之间动态切换：对称多处理（SMP）和不对称多处理（ASMP）。 系统使用某些标准确定何时切换以提高功耗或性能。 控制器可以在两种模式之间进行控制和快速切换。 在接收到切换命令以在SMP和ASMP之间切换时，执行一系列或一系列动作以将电源和CPU /存储器时钟控制到多个处理器和高速缓冲存储器。