公开(公告)号：US09196475B2

公开(公告)日：2015-11-24

申请号：US14253906

申请日：2014-04-16

申请人： GLOBALFOUNDRIES, Inc. ,  Intermolecular, Inc.

发明人： Bongki Lee ,  Paul Besser ,  Kevin Kashefi ,  Olov Karlsson ,  Ashish Bodke ,  Ratsamee Limdulpaiboon ,  Divya Pisharoty ,  Nobi Fuchigami

IPC分类号： H01L23/48 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

CPC分类号： H01L21/02181 ,  H01L21/02164 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

摘要翻译： 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括在FET区域中形成电介质氧化物材料的中间层并覆盖在半导体衬底上。 沉积在中间层上方的高K电介质层。 氟被并入到中间层和/或高K电介质层中。

公开(公告)号：US09607904B2

公开(公告)日：2017-03-28

申请号：US14094691

申请日：2013-12-02

申请人： Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

发明人： Albert Sanghyup Lee ,  Paul Besser ,  Kisik Choi ,  Edward L Haywood ,  Hoon Kim ,  Salil Mujumdar

IPC分类号： H01L21/28 ,  H01L21/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/94

CPC分类号： H01L22/10 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28194 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/94

摘要： ALD of HfxAlyCz films using hafnium chloride (HfCl4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfCl4 pulse time allows for control of the Al % incorporation in the HfxAlyCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxAlyCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ˜4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.

公开(公告)号：US20160093711A1

公开(公告)日：2016-03-31

申请号：US14315079

申请日：2014-06-25

申请人： Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

发明人： Zhendong Hong ,  Paul Besser ,  Kisik Choi ,  Amol Joshi ,  Olov Karlsson ,  Susie Tzeng

IPC分类号： H01L29/49 ,  H01L21/285 ,  H01L29/423 ,  H01L21/28

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

摘要： Devices with lightly-doped semiconductor channels (e.g., FinFETs) need mid-gap (˜4.6-4.7 eV) work-function layers, preferably with low resistivity and a wide process window, in the gate stack. Tantalum carbide (TaC) has a mid-gap work function that is insensitive to thickness. TaC can be deposited with good adhesion on high-k materials or on optional metal-nitride cap layers. TaC can also serve as the fill metal, or it can be used with other fills such as tungsten (W) or aluminum (Al). The TaC may be sputtered from a TaC target, deposited by ALD or CVD using TaCl4 and TMA, or produced by methane treatment of deposited Ta. Al may be added to tune the threshold voltage.

摘要翻译： 具有轻掺杂半导体通道（例如，FinFET）的器件在栅极堆叠中需要中间隙（〜4.6-6.7eV）的功函数层，优选地具有低电阻率和宽的工艺窗口。 碳化钽（TaC）具有对厚度不敏感的中间间隙功能。 可以在高k材料或任选的金属氮化物盖层上沉积具有良好粘附性的TaC。 TaC也可以作为填充金属，也可以与钨（W）或铝（Al）等其他填料一起使用。 TaC可以从TaC靶溅射，通过ALD或CVD使用TaCl4和TMA沉积，或通过沉积的Ta的甲烷处理产生。 可以添加Al来调节阈值电压。

公开(公告)号：US20160035631A1

公开(公告)日：2016-02-04

申请号：US14094691

申请日：2013-12-02

申请人： GLOBALFOUNDRIES, INC. ,  INTERMOLECULAR INC.

发明人： Albert Sanghyup Lee ,  Paul Besser ,  Kisik Choi ,  Edward L Haywood ,  Hoon Kim ,  Salil Mujumdar

IPC分类号： H01L21/66 ,  H01L21/28

CPC分类号： H01L22/10 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28194 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/94

摘要： ALD of HfxAlyCz films using hafnium chloride (HfCl4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfCl4 pulse time allows for control of the Al % incorporation in the HfxAlyCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxAlyCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ˜4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.

摘要翻译： 使用氯化铪（HfCl4）和三甲基铝（TMA）前体的HfxAlyCz膜的ALD可与后沉积退火工艺和ALD衬垫组合以控制高k金属栅极器件中的器件特性。 HfCl 4脉冲时间的变化允许控制HfxAlyCz膜中的Al％掺入在10-13％的范围内。 组合工艺工具可用于各种材料堆的快速电气和材料表征。 金属氧化物半导体电容器（MOSCAP）器件中具有HfxAlyCz功函数层与ALD沉积HfO 2高k栅极电介质层耦合的有效功函数（EWF）被定义为〜4.6eV的中间间隙。 因此，HfxAlyCz是有希望的金属栅极功能材料，允许调谐预期的多Vth集成电路（IC）器件的器件阈值电压（Vth）。

公开(公告)号：US20150303057A1

公开(公告)日：2015-10-22

申请号：US14253906

申请日：2014-04-16

申请人： GLOBALFOUNDRIES, Inc. ,  Intermolecular, Inc.

发明人： Bongki Lee ,  Paul Besser ,  Kevin Kashefi ,  Olov Karlsson ,  Ashish Bodke ,  Ratsamee Limdulpaiboon ,  Divya Pisharoty ,  Nobi Fuchigami

IPC分类号： H01L21/02 ,  H01L29/51 ,  H01L21/28

CPC分类号： H01L21/02181 ,  H01L21/02164 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

摘要翻译： 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括在FET区域中形成电介质氧化物材料的中间层并覆盖在半导体衬底上。 沉积在中间层上方的高K电介质层。 氟被并入到中间层和/或高K电介质层中。

公开(公告)号：US20160181380A1

公开(公告)日：2016-06-23

申请号：US14576597

申请日：2014-12-19

申请人： Intermolecular Inc. ,  Global Foundries, Inc.

发明人： Amol Joshi ,  Sean Barstow ,  Paul Besser ,  Ashish Bodke ,  Guillaume Bouche ,  Nobumichi Fuchigami ,  Zhendong Hong ,  Shaoming Koh ,  Albert Sanghyup Lee ,  Salil Mujumdar ,  Abhijit Pethe ,  Mark Victor Raymond

IPC分类号： H01L29/417 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L21/28568 ,  H01L21/02186 ,  H01L21/02362 ,  H01L21/28512 ,  H01L21/76831 ,  H01L21/76843 ,  H01L29/47 ,  H01L29/66643 ,  H01L29/78 ,  H01L29/7839

摘要： Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.

摘要翻译： 本文提供的实施例描述了用于形成半导体器件的系统和方法。 提供半导体衬底。 源极区和漏极区形成在半导体衬底上。 在源极区域和漏极区域之间形成栅电极。 在源极区域和漏极区域中的至少一个上方形成接触。 触点包括形成在半导体衬底之上的绝缘层，形成在绝缘层之上的界面层以及形成在界面层之上的金属层。 界面层可用作绝缘层的材料和金属层的材料之间的屏障，减小了绝缘层的材料与金属层的材料之间的电阻或其组合。

公开(公告)号：US20140187051A1

公开(公告)日：2014-07-03

申请号：US13727818

申请日：2012-12-27

申请人： Intermolecular Inc.

发明人： Joanna Wasyluk ,  Paul Besser ,  Stephen Kronholz ,  Gregory Nowling ,  James Schaeffer

IPC分类号： H01L21/306

CPC分类号： H01L21/32134 ,  H01L29/66545

摘要： A method for removing poly-silicon dummy gate structures using an ammonium hydroxide-hydrogen peroxide-water (APM) solution with concentrations between 1:10:20 and 1:1:2 and at temperatures between 20 C and 80 C for times between 1 minute and 60 minutes.

摘要翻译： 一种使用氢氧化铵 - 过氧化氢 - 水（APM）溶液去除多硅虚拟栅极结构的方法，浓度为1:10:20至1:1:2，温度为20℃至80℃之间的时间为1 分钟和60分钟。