公开(公告)号：US20160181380A1

公开(公告)日：2016-06-23

申请号：US14576597

申请日：2014-12-19

申请人： Intermolecular Inc. ,  Global Foundries, Inc.

发明人： Amol Joshi ,  Sean Barstow ,  Paul Besser ,  Ashish Bodke ,  Guillaume Bouche ,  Nobumichi Fuchigami ,  Zhendong Hong ,  Shaoming Koh ,  Albert Sanghyup Lee ,  Salil Mujumdar ,  Abhijit Pethe ,  Mark Victor Raymond

IPC分类号： H01L29/417 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L21/28568 ,  H01L21/02186 ,  H01L21/02362 ,  H01L21/28512 ,  H01L21/76831 ,  H01L21/76843 ,  H01L29/47 ,  H01L29/66643 ,  H01L29/78 ,  H01L29/7839

摘要： Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.

摘要翻译： 本文提供的实施例描述了用于形成半导体器件的系统和方法。 提供半导体衬底。 源极区和漏极区形成在半导体衬底上。 在源极区域和漏极区域之间形成栅电极。 在源极区域和漏极区域中的至少一个上方形成接触。 触点包括形成在半导体衬底之上的绝缘层，形成在绝缘层之上的界面层以及形成在界面层之上的金属层。 界面层可用作绝缘层的材料和金属层的材料之间的屏障，减小了绝缘层的材料与金属层的材料之间的电阻或其组合。

公开(公告)号：US08836002B2

公开(公告)日：2014-09-16

申请号：US13738794

申请日：2013-01-10

申请人： Intermolecular, Inc. ,  Elpida Memory, Inc

发明人： Karthik Ramani ,  Hanhong Chen ,  Wim Deweerd ,  Nobumichi Fuchigami ,  Hiroyuki Ode

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01G4/12 ,  H01G4/33 ,  H01L49/02

CPC分类号： H01L28/40 ,  H01G4/1218 ,  H01G4/33 ,  H01L28/60 ,  H01L28/75 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002

摘要： A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

公开(公告)号：US20140084236A1

公开(公告)日：2014-03-27

申请号：US14091594

申请日：2013-11-27

申请人： Intermolecular Inc.

发明人： Nobumichi Fuchigami ,  Pragati KUMAR ,  Prashant B. Phatak

IPC分类号： H01L45/00

CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

摘要： ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.

公开(公告)号：US20150146341A1

公开(公告)日：2015-05-28

申请号：US14092431

申请日：2013-11-27

申请人： GLOBALFOUNDRIES, Inc. ,  Intermolecular Inc.

发明人： Nobumichi Fuchigami ,  David Paul Brunco ,  Karthik Ramani ,  Dina Triyoso

IPC分类号： H01G4/10 ,  C23C16/455 ,  H01G4/30

CPC分类号： H01G4/10 ,  C23C16/403 ,  C23C16/405 ,  C23C16/45525 ,  H01G4/085 ,  H01G4/1281 ,  H01G4/306 ,  H01G4/33 ,  H01L28/40

摘要： A thin sub-layer ( 12) host material. The sub-layer may be formed by atomic layer deposition (ALD). The layer and sub-layer are annealed to form a composite dielectric layer. The host material crystallizes, but the crystalline lattice and grain boundaries are disrupted near the impurity sub-layer, impeding the migration of electrons. The impurity may be a material with a lower dielectric constant than the high-k material, added in such a small relative amount that the composite dielectric is still high-k. Metal-insulator-metal capacitors may be fabricated by forming the composite dielectric layer between two electrodes.

摘要翻译： 在高k（k> 12）主体材料的较厚层（〜30-100）的下面，上方或内部形成杂质的薄亚层（<15Å）。 子层可以通过原子层沉积（ALD）形成。 层和子层进行退火以形成复合介电层。 主体材料结晶，但晶格和晶界在杂质子层附近被破坏，阻碍了电子迁移。 杂质可以是具有比高k材料低的介电常数的材料，以如此小的相对量添加复合电介质仍然高k。 可以通过在两个电极之间形成复合介电层来制造金属 - 绝缘体 - 金属电容器。

公开(公告)号：US20140361236A1

公开(公告)日：2014-12-11

申请号：US14467902

申请日：2014-08-25

申请人： Intermolecular Inc.

发明人： Nobumichi Fuchigami ,  Pragati Kumar ,  Prashant B. Phatak

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

摘要： ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.

摘要翻译： 描述用于形成非易失性电阻式切换存储器的ALD处理技术。 在一个实施例中，一种方法包括在衬底上形成第一电极，保持小于100℃的原子层沉积（ALD）工艺的基座温度，在第一电极上形成至少一个金属氧化物层，其中形成 所述至少一个金属氧化物层使用ALD工艺，使用小于20秒的吹扫持续时间，并在所述至少一个金属氧化物层上形成第二电极。

公开(公告)号：US08847190B2

公开(公告)日：2014-09-30

申请号：US14091594

申请日：2013-11-27

申请人： Intermolecular Inc.

发明人： Nobumichi Fuchigami ,  Pragati Kumar ,  Prashant B Phatak

IPC分类号： H01L29/02 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

摘要： ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.

公开(公告)号：US09252360B2

公开(公告)日：2016-02-02

申请号：US14467902

申请日：2014-08-25

申请人： Intermolecular Inc.

发明人： Nobumichi Fuchigami ,  Pragati Kumar ,  Prashant B Phatak

IPC分类号： H01L21/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

摘要： ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.

公开(公告)号：US08737036B2

公开(公告)日：2014-05-27

申请号：US13657782

申请日：2012-10-22

申请人： Intermolecular, Inc.

发明人： Hanhong Chen ,  Nobumichi Fuchigami ,  Imran Hashim ,  Edward L. Haywood ,  Pragati Kumar ,  Sandra G. Malhotra ,  Monica Sawkar Mathur ,  Prashant B. Phatak ,  Sunil Shanker

IPC分类号： H01G4/30

CPC分类号： H01G4/1218 ,  C23C16/405 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3142 ,  H01L28/40

摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

摘要翻译： 本公开内容提供（a）制造基于氧化钛的氧化物层（例如电介质层）的方法，以抑制锐钛矿相氧化钛的形成和（b）相关的器件和结构。 使用底部电极（或其他基底）的臭氧预处理随后进行ALD工艺来形成金属 - 绝缘体 - 金属（“MIM”）堆叠，以形成根植于使用含酰胺的前体的TiO 2电介质。 在ALD工艺之后，氧化退火工艺的应用热度足以愈合TiO2电介质中的缺陷，并降低TiO2和电极之间的界面态; 选择退火温度以使其不那么热，以致破坏BEL表面粗糙度。 进一步的工艺变型可以包括在ALD工艺期间掺杂氧化钛，基座加热至275-300摄氏度，对于BEL使用铂或钌，对于每个ALD工艺循环使用多个试剂脉冲的臭氧。 该方法提供高沉积速率，并且所得MIM结构基本上没有与锐钛矿相氧化钛相关的x射线衍射峰。

公开(公告)号：US20130273707A1

公开(公告)日：2013-10-17

申请号：US13911929

申请日：2013-06-06

申请人： Intermolecular Inc.

发明人： Nobumichi Fuchigami ,  Pragati KUMAR ,  Prashant B. Phatak

IPC分类号： H01L45/00

CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

摘要： ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.

摘要翻译： 描述用于形成非易失性电阻式切换存储器的ALD处理技术。 在一个实施例中，一种方法包括在衬底上形成第一电极，保持小于100℃的原子层沉积（ALD）工艺的基座温度，在第一电极上形成至少一个金属氧化物层，其中形成 所述至少一个金属氧化物层使用ALD工艺，使用小于20秒的吹扫持续时间，并在所述至少一个金属氧化物层上形成第二电极。

公开(公告)号：US20130154057A1

公开(公告)日：2013-06-20

申请号：US13738794

申请日：2013-01-10

申请人： Intermolecular, Inc. ,  Elpida Memory, Inc

发明人： Karthik Ramani ,  Hanhong Chen ,  Wim Deweerd ,  Nobumichi Fuchigami ,  Hiroyuki Ode

IPC分类号： H01L49/02

CPC分类号： H01L28/40 ,  H01G4/1218 ,  H01G4/33 ,  H01L28/60 ,  H01L28/75 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002

摘要： A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

摘要翻译： 公开了一种用于制造动态随机存取存储器（DRAM）电容器堆叠的方法，其中堆叠包括第一电极，电介质层和第二电极。 第一电极由导电二元金属化合物形成，并且导电二元金属化合物在还原气氛中退火以促进所需晶体结构的形成。 二元金属化合物可以是金属氧化物。 在还原气氛中退火金属氧化物（即氧化钼）可导致形成具有金红石相晶体结构的第一电极材料（即MoO 2）。 当使用TiO 2作为电介质层时，这有助于金红石相晶体结构的形成。 TiO 2的金红石相具有比其他可能的TiO 2晶体结构更高的k值，从而改善了DRAM电容器的性能。