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    Tantalum carbide metal gate stack for mid-gap work function applications
    2.
    发明申请
    Tantalum carbide metal gate stack for mid-gap work function applications 审中-公开
    用于中间隙功能应用的钽硬质合金金属栅极叠层

    公开(公告)号：US20160093711A1

    公开(公告)日：2016-03-31

    申请号：US14315079

    申请日：2014-06-25

    申请人： Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

    发明人： Zhendong Hong ,  Paul Besser ,  Kisik Choi ,  Amol Joshi ,  Olov Karlsson ,  Susie Tzeng

    IPC分类号： H01L29/49 ,  H01L21/285 ,  H01L29/423 ,  H01L21/28

    CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

    摘要： Devices with lightly-doped semiconductor channels (e.g., FinFETs) need mid-gap (˜4.6-4.7 eV) work-function layers, preferably with low resistivity and a wide process window, in the gate stack. Tantalum carbide (TaC) has a mid-gap work function that is insensitive to thickness. TaC can be deposited with good adhesion on high-k materials or on optional metal-nitride cap layers. TaC can also serve as the fill metal, or it can be used with other fills such as tungsten (W) or aluminum (Al). The TaC may be sputtered from a TaC target, deposited by ALD or CVD using TaCl4 and TMA, or produced by methane treatment of deposited Ta. Al may be added to tune the threshold voltage.

    摘要翻译： 具有轻掺杂半导体通道（例如，FinFET）的器件在栅极堆叠中需要中间隙（〜4.6-6.7eV）的功函数层，优选地具有低电阻率和宽的工艺窗口。 碳化钽（TaC）具有对厚度不敏感的中间间隙功能。 可以在高k材料或任选的金属氮化物盖层上沉积具有良好粘附性的TaC。 TaC也可以作为填充金属，也可以与钨（W）或铝（Al）等其他填料一起使用。 TaC可以从TaC靶溅射，通过ALD或CVD使用TaCl4和TMA沉积，或通过沉积的Ta的甲烷处理产生。 可以添加Al来调节阈值电压。

    Atomic Layer Deposition of HfAlC as a Metal Gate Workfunction Material in MOS Devices
    3.
    发明申请
    Atomic Layer Deposition of HfAlC as a Metal Gate Workfunction Material in MOS Devices 有权
    HfAlC作为MOS器件中金属栅极功能材料的原子层沉积

    公开(公告)号：US20160035631A1

    公开(公告)日：2016-02-04

    申请号：US14094691

    申请日：2013-12-02

    申请人： GLOBALFOUNDRIES, INC. ,  INTERMOLECULAR INC.

    发明人： Albert Sanghyup Lee ,  Paul Besser ,  Kisik Choi ,  Edward L Haywood ,  Hoon Kim ,  Salil Mujumdar

    IPC分类号： H01L21/66 ,  H01L21/28

    CPC分类号： H01L22/10 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28194 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/94

    摘要： ALD of HfxAlyCz films using hafnium chloride (HfCl4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfCl4 pulse time allows for control of the Al % incorporation in the HfxAlyCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxAlyCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ˜4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.

    摘要翻译： 使用氯化铪（HfCl4）和三甲基铝（TMA）前体的HfxAlyCz膜的ALD可与后沉积退火工艺和ALD衬垫组合以控制高k金属栅极器件中的器件特性。 HfCl 4脉冲时间的变化允许控制HfxAlyCz膜中的Al％掺入在10-13％的范围内。 组合工艺工具可用于各种材料堆的快速电气和材料表征。 金属氧化物半导体电容器（MOSCAP）器件中具有HfxAlyCz功函数层与ALD沉积HfO 2高k栅极电介质层耦合的有效功函数（EWF）被定义为〜4.6eV的中间间隙。 因此，HfxAlyCz是有希望的金属栅极功能材料，允许调谐预期的多Vth集成电路（IC）器件的器件阈值电压（Vth）。

    METHODS OF SCALING THICKNESS OF A GATE DIELECTRIC STRUCTURE, METHODS OF FORMING AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUITS
    6.
    发明申请
    METHODS OF SCALING THICKNESS OF A GATE DIELECTRIC STRUCTURE, METHODS OF FORMING AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUITS 有权
    门型电介质结构厚度方法，形成集成电路的方法和集成电路

    公开(公告)号：US20150129972A1

    公开(公告)日：2015-05-14

    申请号：US14080533

    申请日：2013-11-14

    申请人： GLOBALFOUNDRIES, Inc.

    发明人： Kisik Choi

    IPC分类号： H01L21/02 ,  H01L27/092 ,  H01L29/51 ,  H01L21/28

    CPC分类号： H01L29/512 ,  H01L21/28185 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517

    摘要： Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided. A method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir. Annealing extends the interfacial oxide layer into the semiconductor substrate at portions of the semiconductor substrate that underlie the oxygen reservoir to form a regrown interfacial region in or on the semiconductor substrate.

    摘要翻译： 提供了覆盖半导体衬底的栅介质结构的厚度缩小方法，形成集成电路的方法和集成电路。 覆盖半导体衬底的栅介质结构的厚度缩小方法包括提供半导体衬底。 在半导体衬底中或其上形成界面氧化物层。 在界面氧化物层上形成高k电介质层。 在高k电介质层的至少一部分上形成氧储存器。 在氧储存器上形成密封剂层。 包括设置在其上的氧气储存器的半导体基板被退火以通过高k电介质层和来自氧气存储器的界面氧化物层扩散氧。 退火在半导体衬底的位于氧储存器底部的部分处将界面氧化物层延伸到半导体衬底中，以在半导体衬底中或其上形成再生长界面区域。

    METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS
    7.
    发明申请
    METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS 有权
    用于CMOS应用和结果产品的晶体管器件的门结构的方法

    公开(公告)号：US20150061027A1

    公开(公告)日：2015-03-05

    申请号：US14017485

    申请日：2013-09-04

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

    IPC分类号： H01L27/092 ,  H01L21/28

    CPC分类号： H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

    摘要： One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

    摘要翻译： 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

    REPLACEMENT METAL GATE WITH MULITIPLE TITANIUM NITRIDE LATERS
    8.
    发明申请
    REPLACEMENT METAL GATE WITH MULITIPLE TITANIUM NITRIDE LATERS 审中-公开
    更换金属盐与多余的硝酸钛后期

    公开(公告)号：US20140246734A1

    公开(公告)日：2014-09-04

    申请号：US13782106

    申请日：2013-03-01

    申请人： Globalfoundries Inc.

    发明人： Hoon Kim ,  Kisik Choi

    IPC分类号： H01L29/51 ,  H01L29/49 ,  H01L21/28

    CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

    摘要： A semiconductor comprising a multilayer structure which prevents oxidization of the titanium nitride layer that protects a high-K dielectric layer is provided. Replacement metal gates are over the multilayer structure. A sacrificial polysilicon gate structure is deposited first. The sacrificial polysilicon gate structure is then removed, and the various layers of the replacement metal gate structure are deposited in the space previously occupied by the sacrificial polysilicon gate structure.

    摘要翻译： 提供了包括防止保护高K电介质层的氮化钛层的氧化的多层结构的半导体。 替代金属门在多层结构之上。 首先沉积牺牲多晶硅栅极结构。 然后去除牺牲多晶硅栅极结构，并且替换金属栅极结构的各个层沉积在先前由牺牲多晶硅栅极结构占据的空间中。

    SEMICONDUCTOR GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION AND METHOD OF MAKING SAME
    9.
    发明申请
    SEMICONDUCTOR GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION AND METHOD OF MAKING SAME 有权
    用于阈值电压调节的半导体闸门结构及其制造方法

    公开(公告)号：US20140231922A1

    公开(公告)日：2014-08-21

    申请号：US13770493

    申请日：2013-02-19

    申请人： GLOBALFOUNDRIES, INC.

    发明人： Hoon Kim ,  Kisik Choi

    IPC分类号： H01L29/40 ,  H01L29/49

    CPC分类号： H01L29/401 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    摘要： A gate structure of a semiconductor device having a NFET and a PFET, includes a lower layer of a hafnium-based dielectric over the gates of the NFET and PFET, and an upper layer of a lanthanide dielectric. The dielectrics are annealed to mix them above the NFET resulting in a lowered work function, and corresponding threshold voltage reduction. An annealed, relatively thick titanium nitride cap over the mixed dielectric above the NFET gate also lowers the work function and threshold voltage. Above the TiN cap and the hafnium-based dielectric over the PFET gate, is another layer of titanium nitride that has not been annealed. A conducting layer of tungsten covers the structure.

    摘要翻译： 具有NFET和PFET的半导体器件的栅极结构包括在NFET和PFET的栅极上方的基于铪的电介质的下层和镧系元素电介质的上层。 将电介质退火以将其混合在NFET上方，导致降低的功函数和相应的阈值电压降低。 在NFET栅极上方的混合电介质上的退火的较厚的氮化钛盖也降低了功函数和阈值电压。 在PFET栅极上的TiN盖和铪基电介质之上，是未经退火的另一层氮化钛。 钨的导电层覆盖该结构。

    Metal gate structure for midgap semiconductor device and method of making same
    10.
    发明授权
    Metal gate structure for midgap semiconductor device and method of making same 有权
    中间半导体器件的金属栅极结构及其制造方法

    公开(公告)号：US09496143B2

    公开(公告)日：2016-11-15

    申请号：US13670251

    申请日：2012-11-06

    申请人： GLOBALFOUNDRIES, Inc.

    发明人： Hoon Kim ,  Kisik Choi

    IPC分类号： H01L21/02 ,  H01L21/8222 ,  H01L21/28 ,  H01L29/49

    CPC分类号： H01L21/28088 ,  H01L29/4966

    摘要： A PFET-based semiconductor gate structure providing a midgap work function for threshold voltage control between that of a NFET and a PFET is created by including an annealed layer of relatively thick TiN to dominate and shift the overall work function down from that of PFET. The structure has a PFET base covered with a high-k dielectric, a layer of annealed TiN, a layer of unannealed TiN, a thin barrier over the unannealed TiN, and n-type metal over the thin barrier.

    摘要翻译： 通过包括相对较厚的TiN的退火层来支配并将整个功函数从PFET的整个功能转移到底部，从而产生用于在NFET和PFET之间进行阈值电压控制的中隙工作功能的基于PFET的半导体栅极结构。 该结构具有覆盖有高k电介质层，退火TiN层，未退火TiN层，未退火TiN上的薄势垒和薄势垒上的n型金属的PFET基极。