公开(公告)号：US09437443B2

公开(公告)日：2016-09-06

申请号：US13916109

申请日：2013-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Markus Brink ,  Michael A. Guillorn ,  Sebastian U. Engelmann ,  Hiroyuki Miyazoe ,  Adam M. Pyzyna ,  Jeffrey W. Sleight

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/3086 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/3088 ,  H01L21/32139

Abstract: A SIT method includes the following steps. An SIT mandrel material is deposited onto a substrate and formed into a plurality of SIT mandrels. A spacer material is conformally deposited onto the substrate covering a top and sides of each of the SIT mandrels. Atomic Layer Deposition (ALD) is used to deposit the SIT spacer at low temperatures. The spacer material is selected from the group including a metal, a metal oxide, a metal nitride and combinations including at least one of the foregoing materials. The spacer material is removed from all but the sides of each of the SIT mandrels to form SIT sidewall spacers on the sides of each of the SIT mandrels. The SIT mandrels are removed selective to the SIT sidewall spacers revealing a pattern of the SIT sidewall spacers. The pattern of the SIT sidewall spacers is transferred to the underlying stack or substrate.

Abstract translation: SIT方法包括以下步骤。 将SIT芯棒材料沉积到衬底上并形成多个SIT芯棒。 间隔物材料被共形沉积到基底上，覆盖每个SIT心轴的顶部和侧面。 原子层沉积（ALD）用于在低温下沉积SIT间隔物。 间隔材料选自金属，金属氧化物，金属氮化物和包括至少一种前述材料的组合。 隔离材料从每个SIT心轴的所有侧面除去，以在每个SIT心轴的侧面上形成SIT侧壁间隔物。 SIT心轴被选择性地移除到SIT侧壁间隔件上，露出SIT侧壁间隔物的图案。 SIT侧壁间隔物的图案被转移到下面的堆叠或衬底。

公开(公告)号：US20170250111A1

公开(公告)日：2017-08-31

申请号：US15593496

申请日：2017-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Adam M. Pyzyna

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/12 ,  H01L21/74

CPC classification number: H01L21/76879 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/1203

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

公开(公告)号：US10014214B2

公开(公告)日：2018-07-03

申请号：US15593496

申请日：2017-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Adam M. Pyzyna

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/528 ,  H01L27/12 ,  H01L21/74 ,  H01L23/535

CPC classification number: H01L21/76879 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/1203

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

公开(公告)号：US09716036B2

公开(公告)日：2017-07-25

申请号：US14733398

申请日：2015-06-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Adam M. Pyzyna

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L27/12

CPC classification number: H01L21/76879 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/1203

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

公开(公告)号：US20160358852A1

公开(公告)日：2016-12-08

申请号：US14733398

申请日：2015-06-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Adam M. Pyzyna

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/1203

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

Abstract translation: 提供电子设备。 电子器件包括半导体层，设置在半导体层上的电介质层，设置在电介质层上的电路，包括互连电池，第一接触线金属化和第二接触线金属化，第一电力金属化设置在电路内或电路之上 以及设置在至少所述介电层中限定的沟槽中的第二功率金属化。 电子设备还包括绝缘体，其设置成在第一位置处将第二功率金属化与电路和第一功率金属化绝缘，并且允许在第二位置处的第二功率金属化，电路和第一功率金属化之间的电通信。