公开(公告)号：US10002835B2

公开(公告)日：2018-06-19

申请号：US15427156

申请日：2017-02-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Benjamin V. Fasano ,  Michael S. Cranmer ,  Richard F. Indyk ,  Harry Cox ,  Katsuyuki Sakuma ,  Eric D. Perfecto

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5386 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1146 ,  H01L2224/1184 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/157 ,  H01L2924/15717 ,  H01L2924/15738 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014

Abstract: A semiconductor device and a stacked pillar used to interconnect a first semiconductor die and a second semiconductor die are provided. The semiconductor device has a substrate, a splice interposer, a first semiconductor die, a second semiconductor die and first to fourth plurality of pillars. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate. The stacked pillar has a first conductor layer formed on a surface of the first semiconductor die, a first solder layer formed on the first conductor layer, a second conductor layer formed on the first solder layer, and a second solder layer formed on the second conductor layer. The second solder layer is heat-reflowable to attach the stacked pillar to a surface of the second semiconductor.

公开(公告)号：US09633925B1

公开(公告)日：2017-04-25

申请号：US15081403

申请日：2016-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Katsuyuki Sakuma ,  Mukta G. Farooq ,  Jae-Woong Nah

IPC: H01L23/544 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/29

CPC classification number: H01L21/76864 ,  H01L21/563 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473

Abstract: Structures and methods for improving the visualization of alignment marks on an underfill-covered chip. A feature is formed on a chip, and an underfill material is applied to the chip at a wafer level so that the feature is covered the feature. The feature includes a first structural element comprised of a first material and a second structural element comprised of a second material that is electrochemically dissimilar from the first material to provide a galvanic cell effect. Filler particles in the underfill material are caused by the galvanic cell effect to distribute with a first density in a first region over the first structural element and a second region of a second density over the second structural element. The first density in the first region is less than the second density in the second region such that the first region has a lower opacity than the second region.

公开(公告)号：US09607973B1

公开(公告)日：2017-03-28

申请号：US14946162

申请日：2015-11-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Benjamin V. Fasano ,  Michael S. Cranmer ,  Richard F. Indyk ,  Harry Cox ,  Katsuyuki Sakuma ,  Eric D. Perfecto

IPC: H01L21/44 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1146 ,  H01L2224/1184 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/157 ,  H01L2924/15717 ,  H01L2924/15738 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014

Abstract: A method of interconnecting first and second semiconductor dies is provided. A splice interposer is attached to a top surface of a substrate through first pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through second pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through third pillars formed on the bottom surface of the first semiconductor. The second semiconductor die is attached to the top surface of the splice interposer through fourth pillars formed on a bottom surface of the second semiconductor die. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate.