公开(公告)号：US09786751B2

公开(公告)日：2017-10-10

申请号：US15263551

申请日：2016-09-13

Applicant: GlobalFoundries Inc.

Inventor： Brent A. Anderson ,  Jeffrey B. Johnson ,  Edward J. Nowak

IPC: H01L29/78 ,  H01L23/48 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.

公开(公告)号：US10056408B2

公开(公告)日：2018-08-21

申请号：US15335549

申请日：2016-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andres Bryant ,  Jeffrey B. Johnson ,  Effendi Leobandung ,  Tenko Yamashita

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/51

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.

公开(公告)号：US09525069B2

公开(公告)日：2016-12-20

申请号：US14576611

申请日：2014-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andres Bryant ,  Jeffrey B. Johnson ,  Effendi Leobandung ,  Tenko Yamashita

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.

Abstract translation: 一种制造FinFET器件的方法包括：形成具有覆盖掩埋氧化物（BOX）层的半导体层的绝缘体上硅（SOI）衬底; 蚀刻半导体层以在多个翅片结构和BOX层之间形成多个翅片结构和半导体层间隙; 在至少一个栅极区上沉积牺牲栅极，其中栅极区域分离源区和漏区; 在牺牲栅极的垂直侧壁上设置偏置间隔物; 去除牺牲门; 去除所述栅极区域中的半导体层间隙，以防止所述栅极区域中的所述多个翅片结构的合流; 以及制造覆盖栅极区域中的鳍结构的高k电介质金属栅极结构。

公开(公告)号：US20170294385A1

公开(公告)日：2017-10-12

申请号：US15634135

申请日：2017-06-27

Applicant: GlobalFoundries Inc.

Inventor： Brent A. Anderson ,  Jeffrey B. Johnson ,  Edward J. Nowak

IPC: H01L23/528 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.

公开(公告)号：US08987078B2

公开(公告)日：2015-03-24

申请号：US14028957

申请日：2013-09-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Abstract translation: 提供一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构，在栅极结构上方形成层间电介质层，并通过层间介质层形成通向半导体的暴露表面的开口 含有源区和漏区中的至少一个的衬底。 在半导体衬底的暴露表面上形成金属半导体合金接触。 在开口的侧壁上形成至少一个电介质侧壁间隔物。 在与金属半导体合金接触件直接接触的开口内形成互连。

公开(公告)号：US20170047350A1

公开(公告)日：2017-02-16

申请号：US15335549

申请日：2016-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andres Bryant ,  Jeffrey B. Johnson ,  Effendi Leobandung ,  Tenko Yamashita

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/45 ,  H01L29/51 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.

Abstract translation: 一种制造FinFET器件的方法包括：形成具有覆盖掩埋氧化物（BOX）层的半导体层的绝缘体上硅（SOI）衬底; 蚀刻半导体层以在多个翅片结构和BOX层之间形成多个翅片结构和半导体层间隙; 在至少一个栅极区上沉积牺牲栅极，其中栅极区域分离源区和漏区; 在牺牲栅极的垂直侧壁上设置偏置间隔物; 去除牺牲门; 去除所述栅极区域中的半导体层间隙，以防止所述栅极区域中的所述多个翅片结构的合流; 以及制造覆盖栅极区域中的鳍结构的高k电介质金属栅极结构。

公开(公告)号：US09496394B2

公开(公告)日：2016-11-15

申请号：US14523083

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Jeffrey B. Johnson ,  Edward J. Nowak

IPC: H01L21/4763 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/66

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.

Abstract translation: 公开了包括具有低电阻源极/漏极接触和可选地低栅极 - 源极/漏极接触电容的场效应晶体管（FET）的半导体结构。 该结构包括半导体本体，并包含在其中，第一和第二源极/漏极区域和沟道区域。 第一栅极在沟道区域处与半导体本体相邻，并且第二非功能栅极与半导体本体相邻，使得第二源极/漏极区域位于第一和第二栅极之间。 第一和第二源极/漏极触点分别位于第一和源极/漏极区域上。 第二源极/漏极触点比第一源极/漏极触点更宽，因此具有较低的电阻。 此外，第一和第二源极/漏极接触件相对于第一栅极的间隔可以使得第一栅极至第二源极/漏极接触电容等于或小于第一栅极至第一源极/漏极接触 电容。 还公开了相关的形成方法。

公开(公告)号：US10482200B2

公开(公告)日：2019-11-19

申请号：US14146114

申请日：2014-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Samarth Agarwal ,  Abhisek Dixit ,  Jeffrey B. Johnson

IPC: G06F17/50

Abstract: In one embodiment, the invention comprises: defining a first volume in a layer of a semiconductor device; calculating a probability of finding at least one dopant atom in the first volume, based on a dopant distribution of the layer; in the case that the calculated probability is equal to or greater than a pre-determined threshold, defining at least one additional volume in the layer substantially equal to the first volume; and in the case that the calculated probability is less than the pre-determined threshold: aggregating the first volume with a second volume adjacent the first volume, the second volume being substantially equal to the first volume; and recalculating a probability of finding at least one dopant atom in the aggregated first and second volumes, based on the dopant distribution of the layer.

公开(公告)号：US10269707B2

公开(公告)日：2019-04-23

申请号：US15634135

申请日：2017-06-27

Applicant: GlobalFoundries Inc.

Inventor： Brent A. Anderson ,  Jeffrey B. Johnson ,  Edward J. Nowak

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L23/485 ,  H01L23/535 ,  H01L29/78 ,  H01L23/528

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.

公开(公告)号：US20160380065A1

公开(公告)日：2016-12-29

申请号：US15263551

申请日：2016-09-13

Applicant: GlobalFoundries Inc.

Inventor： Brent A. Anderson ,  Jeffrey B. Johnson ,  Edward J. Nowak

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.