公开(公告)号：US20170005085A1

公开(公告)日：2017-01-05

申请号：US15264885

申请日：2016-09-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jin Cai ,  Effendi Leobandung ,  Tak H. Ning

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/66545

Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.

Abstract translation: 形成半导体结构的方法包括在位于第一CMOS器件的侧壁间隔件之间的第一凹槽内以及位于第二CMOS器件的侧壁间隔物之间​​的第二凹槽内沉积高k电介质层。 在高k电介质层上沉积虚拟氮化钛层。 接下来，从第二CMOS器件的第二凹部去除高k电介质层和虚拟氮化钛层。 在第一凹槽和第二凹槽中沉积硅帽层，硅帽层位于第一CMOS器件中的高k电介质层和虚拟氮化钛层的上方。 随后，将掺杂剂注入到位于第二CMOS器件的第二凹槽中的硅帽层中。

公开(公告)号：US09263583B2

公开(公告)日：2016-02-16

申请号：US14052924

申请日：2013-10-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jin Cai ,  Effendi Leobandung ,  Tak H. Ning

IPC: H01L29/78 ,  H01L29/73 ,  H01L21/8222 ,  H01L21/8248

CPC classification number: H01L29/785 ,  H01L21/8222 ,  H01L21/823821 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/845 ,  H01L27/0623 ,  H01L27/0924 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/73 ,  H01L29/735

Abstract: A method of forming a semiconductor structure that includes forming a first recess and a second recess between a first pair of sidewall spacers and a second pair of sidewall spacers respectively, the first and second pair of sidewall spacers surrounding a fin on top of a buried dielectric layer, the fin is formed from a top most semiconductor layer of a semiconductor-on-insulator substrate. A high-k dielectric layer is deposited within the first and second recesses and a dummy titanium nitride layer is deposited on the high-k dielectric layer. The high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess and a silicon cap layer is deposited within the first and second recesses. Next, dopants are implanted into the silicon cap layer in the second recess without implanting dopants into the silicon cap layer in the first recess to form a BJT device.

Abstract translation: 一种形成半导体结构的方法，包括在第一对侧壁间隔件和第二对侧壁间隔物之间​​分别形成第一凹部和第二凹槽，所述第一和第二对侧壁间隔件围绕埋在电介质顶部的翅片 层，由绝缘体上半导体衬底的最上半导体层形成鳍。 高k电介质层沉积在第一和第二凹槽内，并且在高k电介质层上沉积虚拟氮化钛层。 从第二凹部去除高k电介质层和虚拟氮化钛层，并且在第一和第二凹槽内沉积硅帽层。 接下来，将掺杂剂注入到第二凹槽中的硅帽层中，而不将掺杂剂注入到第一凹槽中的硅帽层中以形成BJT器件。

公开(公告)号：US10192864B2

公开(公告)日：2019-01-29

申请号：US15264885

申请日：2016-09-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jin Cai ,  Effendi Leobandung ,  Tak H. Ning

IPC: H01L27/06 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/66

Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.

公开(公告)号：US20170047350A1

公开(公告)日：2017-02-16

申请号：US15335549

申请日：2016-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andres Bryant ,  Jeffrey B. Johnson ,  Effendi Leobandung ,  Tenko Yamashita

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/45 ,  H01L29/51 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.

Abstract translation: 一种制造FinFET器件的方法包括：形成具有覆盖掩埋氧化物（BOX）层的半导体层的绝缘体上硅（SOI）衬底; 蚀刻半导体层以在多个翅片结构和BOX层之间形成多个翅片结构和半导体层间隙; 在至少一个栅极区上沉积牺牲栅极，其中栅极区域分离源区和漏区; 在牺牲栅极的垂直侧壁上设置偏置间隔物; 去除牺牲门; 去除所述栅极区域中的半导体层间隙，以防止所述栅极区域中的所述多个翅片结构的合流; 以及制造覆盖栅极区域中的鳍结构的高k电介质金属栅极结构。

公开(公告)号：US09478534B2

公开(公告)日：2016-10-25

申请号：US14048131

申请日：2013-10-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jin Cai ,  Effendi Leobandung ,  Tak H. Ning

IPC: H01L21/8249 ,  H01L27/06

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/66545

Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.

Abstract translation: 形成半导体结构的方法包括在位于第一CMOS器件的侧壁间隔件之间的第一凹槽内以及位于第二CMOS器件的侧壁间隔物之间​​的第二凹槽内沉积高k电介质层。 在高k电介质层上沉积虚拟氮化钛层。 接下来，从第二CMOS器件的第二凹部去除高k电介质层和虚拟氮化钛层。 在第一凹槽和第二凹槽中沉积硅帽层，硅帽层位于第一CMOS器件中的高k电介质层和虚拟氮化钛层的上方。 随后，将掺杂剂注入到位于第二CMOS器件的第二凹槽中的硅帽层中。

公开(公告)号：US09257545B2

公开(公告)日：2016-02-09

申请号：US14024729

申请日：2013-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Effendi Leobandung

IPC: H01L29/775 ,  H01L29/66

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78654

Abstract: A method of forming a semiconductor structure including forming a stack of layers on a top surface of a substrate, the stack of layers including alternating layers of a semiconductor material and a sacrificial material, where a bottommost layer of the stack of layers is a top semiconductor layer of the substrate, patterning a plurality of material stacks from the stack of layers, each material stack including an alternating stack of a plurality of nanowire channels and a plurality of sacrificial spacers, the plurality of nanowire channels including the semiconductor material, and the plurality of sacrificial spacers including the sacrificial material, and removing at least one of the plurality of nanowire channels from at least one of the plurality of material stacks without removing one or more of the plurality of nanowire channels from an adjacent material stack.

Abstract translation: 一种形成半导体结构的方法，包括在衬底的顶表面上形成一层叠层，所述叠层包括半导体材料和牺牲材料的交替层，其中层的最底层是顶部半导体 层，从堆叠图案化多个材料堆叠，每个材料堆叠包括多个纳米线通道和多个牺牲间隔物的交替堆叠，所述多个纳米线通道包括半导体材料，并且所述多个纳米线通道包括半导体材料 包括牺牲材料的牺牲间隔物，以及从多个材料堆叠中的至少一个去除多个纳米线通道中的至少一个，而不从相邻的材料堆叠中移除多个纳米线通道中的一个或多个。

公开(公告)号：US10056408B2

公开(公告)日：2018-08-21

申请号：US15335549

申请日：2016-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andres Bryant ,  Jeffrey B. Johnson ,  Effendi Leobandung ,  Tenko Yamashita

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/51

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.

公开(公告)号：US09711648B1

公开(公告)日：2017-07-18

申请号：US15232164

申请日：2016-08-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Effendi Leobandung ,  Chung-Hsun Lin ,  Amlan Majumdar ,  Yanning Sun

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78603 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66522 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: A semiconductor structure is provided that includes a channel material portion composed of a III-V compound semiconductor located on a mesa portion of a substrate. A dielectric spacer structure is located on each sidewall surface of the channel material portion and each sidewall surface of the mesa portion of the substrate. The dielectric spacer structure has a height that is greater than a height of the channel material portion. An isolation structure is located on each dielectric spacer structure, wherein a sidewall edge of the isolation structure is located between an innermost sidewall surface and an outermost sidewall surface of the dielectric spacer structure.

公开(公告)号：US09525069B2

公开(公告)日：2016-12-20

申请号：US14576611

申请日：2014-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andres Bryant ,  Jeffrey B. Johnson ,  Effendi Leobandung ,  Tenko Yamashita

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.

Abstract translation: 一种制造FinFET器件的方法包括：形成具有覆盖掩埋氧化物（BOX）层的半导体层的绝缘体上硅（SOI）衬底; 蚀刻半导体层以在多个翅片结构和BOX层之间形成多个翅片结构和半导体层间隙; 在至少一个栅极区上沉积牺牲栅极，其中栅极区域分离源区和漏区; 在牺牲栅极的垂直侧壁上设置偏置间隔物; 去除牺牲门; 去除所述栅极区域中的半导体层间隙，以防止所述栅极区域中的所述多个翅片结构的合流; 以及制造覆盖栅极区域中的鳍结构的高k电介质金属栅极结构。

公开(公告)号：US20160225916A1

公开(公告)日：2016-08-04

申请号：US15015766

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Effendi Leobandung

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78654

Abstract: A method of forming a semiconductor structure including forming a stack of layers on a top surface of a substrate, the stack of layers including alternating layers of a semiconductor material and a sacrificial material, where a bottommost layer of the stack of layers is a top semiconductor layer of the substrate, patterning a plurality of material stacks from the stack of layers, each material stack including an alternating stack of a plurality of nanowire channels and a plurality of sacrificial spacers, the plurality of nanowire channels including the semiconductor material, and the plurality of sacrificial spacers including the sacrificial material, and removing at least one of the plurality of nanowire channels from at least one of the plurality of material stacks without removing one or more of the plurality of nanowire channels from an adjacent material stack.