公开(公告)号：US10049909B2

公开(公告)日：2018-08-14

申请号：US15432560

申请日：2017-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Garant ,  Jonathan H. Griffith ,  Brittany L. Hedrick ,  Edmund J. Sprogis

IPC: H01L21/683 ,  B32B37/24 ,  B32B38/10 ,  B81C1/00

Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.

公开(公告)号：US20170154800A1

公开(公告)日：2017-06-01

申请号：US15432560

申请日：2017-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Garant ,  Jonathan H. Griffith ,  Brittany L. HEDRICK ,  Edmund J. Sprogis

IPC: H01L21/683 ,  B32B38/10 ,  B32B37/24

CPC classification number: H01L21/6835 ,  B32B37/24 ,  B32B38/10 ,  B32B2037/246 ,  B32B2315/08 ,  B32B2457/14 ,  B81C1/00666 ,  B81C2201/0167 ,  H01L2221/68304 ,  H01L2221/68327

Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.

公开(公告)号：US09805977B1

公开(公告)日：2017-10-31

申请号：US15176598

申请日：2016-06-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vijay Sukumaran ,  Thuy L. Tran-Quinn ,  Jorge A. Lubguban ,  John J. Garant

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/48 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/321

CPC classification number: H01L21/76898 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/481

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a front side and back side opposing the front side, the integrated circuit structure comprising: a through-silicon-via (TSV) at least partially within a dielectric layer extending away from the front side; a first metal adjacent to the TSV and within the dielectric layer, the first metal being substantially surrounded by a first seed layer; a conductive pad over the first metal and the TSV and extending away from the front side, wherein the conductive pad provides electrical connection between the TSV and the first metal and includes a second seed layer substantially surrounding a second metal, wherein the second seed layer separates the second metal from the first metal and the TSV.