公开(公告)号：US09236261B2

公开(公告)日：2016-01-12

申请号：US14242215

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kevin Kashefi ,  Ashish Bodke

IPC: H01L21/3205 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L21/28088 ,  H01L21/28562 ,  H01L21/76846 ,  H01L29/4966 ,  H01L29/66568 ,  H01L29/6659

Abstract: Transistors having a work function layer and methods of fabricating thereof are disclosed herein. The work function layer includes aluminum and titanium layers which are deposited in separate atomic layer deposition (ALD) operations. The depositions of the titanium layers and the aluminum layers may be separated by a purge operation or even performed in different ALD chambers. The work function layer may include alternating sets of titanium layers and sets of aluminum layers, thereby forming a nanolaminate structure. As such, a ratio of titanium to aluminum may be controlled and varied as needed throughout the thickness of the work function layer. For example, the work function layer may be titanium rich at the surface facing the gate dielectric in order to reduce or prevent diffusion of aluminum into the gate dielectric.

Abstract translation: 具有功函数层的晶体管及其制造方法在此公开。 工作功能层包括以单独的原子层沉积（ALD）操作沉积的铝和钛层。 钛层和铝层的沉积可以通过吹扫操作分离，甚至可以在不同的ALD室中进行。 功函数层可以包括交替的钛层和一组铝层，由此形成纳米层状结构。 因此，可以根据需要在功函数层的厚度上控制和改变钛与铝的比例。 例如，工作功能层可以在面向栅极电介质的表面处富含钛，以便减少或防止铝扩散到栅极电介质中。

公开(公告)号：US09196475B2

公开(公告)日：2015-11-24

申请号：US14253906

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES, Inc. ,  Intermolecular, Inc.

Inventor： Bongki Lee ,  Paul Besser ,  Kevin Kashefi ,  Olov Karlsson ,  Ashish Bodke ,  Ratsamee Limdulpaiboon ,  Divya Pisharoty ,  Nobi Fuchigami

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/02181 ,  H01L21/02164 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括在FET区域中形成电介质氧化物材料的中间层并覆盖在半导体衬底上。 沉积在中间层上方的高K电介质层。 氟被并入到中间层和/或高K电介质层中。

公开(公告)号：US20150093914A1

公开(公告)日：2015-04-02

申请号：US14044514

申请日：2013-10-02

Applicant: Intermolecular ,  GLOBALFOUNDRIES, Inc.

Inventor： Bin Yang ,  Abhijit Pethe ,  Albert Lee ,  Amol Joshi ,  Ashish Bodke ,  Kevin Kashefi ,  Salil Mujumdar

IPC: H01L21/02

CPC classification number: H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/2807 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeOx layer formed thereon and exposing the semiconductor substrate to first and second atomic layer deposition (ALD) processes. The first ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a first oxygen-containing precursor. The second ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a second oxygen-containing precursor.

Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括形成在其上的GeO x层的锗基半导体衬底，并将半导体衬底暴露于第一和第二原子层沉积（ALD）工艺。 第一ALD工艺包括将半导体衬底暴露于包含铝的第一气态前体，并将半导体衬底暴露于包含第一含氧前体的第二气态前体。 第二ALD工艺包括将半导体衬底暴露于包含铝的第一气态前体，并将半导体衬底暴露于包含第二含氧前体的第二气态前体。

公开(公告)号：US20150093889A1

公开(公告)日：2015-04-02

申请号：US14044376

申请日：2013-10-02

Applicant: Intermolecular ,  GLOBALFOUNDRIES, Inc.

Inventor： Bin Yang ,  Abhijit Pethe ,  Albert Lee ,  Amol Joshi ,  Ashish Bodke ,  Kevin Kashefi ,  Salil Mujumdar

IPC: H01L29/51

CPC classification number: H01L29/517 ,  H01L21/28255 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeOx layer formed thereon having a first thickness, removing a portion of the GeOx layer by exposing the semiconductor substrate to a hydrogen-plasma dry etch so as to reduce the first thickness of the GeOx layer to a second thickness, and depositing a high-k material over the GeOx layer of the semiconductor substrate.

Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：提供锗基半导体衬底，其包含在其上形成的具有第一厚度的GeO x层，通过将半导体衬底暴露于氢等离子体干法蚀刻来去除GeOx层的一部分，从而 以将GeOx层的第一厚度减小到第二厚度，以及在半导体衬底的GeO x层上沉积高k材料。

公开(公告)号：US20150380309A1

公开(公告)日：2015-12-31

申请号：US14315718

申请日：2014-06-26

Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

Inventor： Salil Mujumdar ,  Amol Joshi ,  Kevin Kashefi ,  Albert Sanghyup Lee ,  Abhijit Pethe ,  Bin Yang

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L29/517 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/285 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal-insulator-semiconductor (MIS) contacts for germanium and its alloys include insulator layers of oxygen-deficient metal oxide deposited by atomic layer deposition (ALD). The oxygen deficiency reduces the tunnel barrier resistance of the insulator layer while maintaining the layer's ability to prevent Fermi-level pinning at the metal/semiconductor interface. The oxygen deficiency is controlled by optimizing one or more ALD parameters such as shortened oxidant pulses, use of less-reactive oxidants such as water, heating the substrate during deposition, TMA “cleaning” of native oxide before deposition, and annealing after deposition. Secondary factors include reduced process-chamber pressure, cooled oxidant, and shortened pulses of the metal precursor.

Abstract translation: 用于锗及其合金的金属 - 绝缘体 - 半导体（MIS）触点包括通过原子层沉积（ALD）沉积的缺氧金属氧化物的绝缘体层。 缺氧会降低绝缘体层的隧道势垒阻力，同时保持层在金属/半导体界面处防止费米能级钉扎的能力。 通过优化一个或多个ALD参数，例如缩短的氧化剂脉冲，使用较少反应性的氧化剂例如水，在沉积期间加热衬底，在沉积之前对自然氧化物进行TMA“清洁”，以及沉积后的退火来优化一个或多个ALD参数来控制氧缺乏。 次要因素包括降低的处理室压力，冷却的氧化剂和金属前体的缩短的脉冲。

公开(公告)号：US20150279680A1

公开(公告)日：2015-10-01

申请号：US14242215

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin Kashefi ,  Ashish Bodke

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/285 ,  H01L29/49

CPC classification number: H01L21/28088 ,  H01L21/28562 ,  H01L21/76846 ,  H01L29/4966 ,  H01L29/66568 ,  H01L29/6659

Abstract: Transistors having a work function layer and methods of fabricating thereof are disclosed herein. The work function layer includes aluminum and titanium layers which are deposited in separate atomic layer deposition (ALD) operations. The depositions of the titanium layers and the aluminum layers may be separated by a purge operation or even performed in different ALD chambers. The work function layer may include alternating sets of titanium layers and sets of aluminum layers, thereby forming a nanolaminate structure. As such, a ratio of titanium to aluminum may be controlled and varied as needed throughout the thickness of the work function layer. For example, the work function layer may be titanium rich at the surface facing the gate dielectric in order to reduce or prevent diffusion of aluminum into the gate dielectric.

Abstract translation: 具有功函数层的晶体管及其制造方法在此公开。 功函数层包括以单独的原子层沉积（ALD）操作沉积的铝和钛层。 钛层和铝层的沉积可以通过吹扫操作分离，甚至可以在不同的ALD室中进行。 功函数层可以包括交替的钛层和一组铝层，由此形成纳米层状结构。 因此，可以根据需要在功函数层的厚度上控制和改变钛与铝的比例。 例如，工作功能层可以在面向栅极电介质的表面处富含钛，以便减少或防止铝扩散到栅极电介质中。

公开(公告)号：US20150093887A1

公开(公告)日：2015-04-02

申请号：US14253668

申请日：2014-04-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Bin Yang ,  Shurong Liang ,  Kristina Young-Fisher ,  Kevin Kashefi ,  Amol Joshi ,  Salil Mujumdar ,  Abhijit Pethe ,  Albert Lee ,  Ashish Bodke

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/28255 ,  H01L21/02046 ,  H01L21/2807 ,  H01L21/31116 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate including a GeOx layer formed thereon having a first thickness, removing a portion of the GeOx layer by exposing the semiconductor substrate to a NF3/NH3 plasma dry etch so as to reduce the first thickness of the GeOx layer to a second thickness, and depositing a high-k material over the GeOx layer of the semiconductor substrate.

Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供锗基半导体衬底，其包括在其上形成的具有第一厚度的GeO x层，通过将半导体衬底暴露于NF3 / NH3等离子体干蚀刻来去除GeOx层的一部分 以便将GeO x层的第一厚度减小到第二厚度，并且在半导体衬底的GeO x层上沉积高k材料。

公开(公告)号：US20150303057A1

公开(公告)日：2015-10-22

申请号：US14253906

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES, Inc. ,  Intermolecular, Inc.

Inventor： Bongki Lee ,  Paul Besser ,  Kevin Kashefi ,  Olov Karlsson ,  Ashish Bodke ,  Ratsamee Limdulpaiboon ,  Divya Pisharoty ,  Nobi Fuchigami

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/02181 ,  H01L21/02164 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括在FET区域中形成电介质氧化物材料的中间层并覆盖在半导体衬底上。 沉积在中间层上方的高K电介质层。 氟被并入到中间层和/或高K电介质层中。