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    Deposition of titanium-aluminum layers
    2.
    发明授权
    Deposition of titanium-aluminum layers 有权
    沉积钛 - 铝层

    公开(公告)号：US09236261B2

    公开(公告)日：2016-01-12

    申请号：US14242215

    申请日：2014-04-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Kevin Kashefi ,  Ashish Bodke

    IPC: H01L21/3205 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/285

    CPC classification number: H01L21/28088 ,  H01L21/28562 ,  H01L21/76846 ,  H01L29/4966 ,  H01L29/66568 ,  H01L29/6659

    Abstract: Transistors having a work function layer and methods of fabricating thereof are disclosed herein. The work function layer includes aluminum and titanium layers which are deposited in separate atomic layer deposition (ALD) operations. The depositions of the titanium layers and the aluminum layers may be separated by a purge operation or even performed in different ALD chambers. The work function layer may include alternating sets of titanium layers and sets of aluminum layers, thereby forming a nanolaminate structure. As such, a ratio of titanium to aluminum may be controlled and varied as needed throughout the thickness of the work function layer. For example, the work function layer may be titanium rich at the surface facing the gate dielectric in order to reduce or prevent diffusion of aluminum into the gate dielectric.

    Abstract translation: 具有功函数层的晶体管及其制造方法在此公开。 工作功能层包括以单独的原子层沉积（ALD）操作沉积的铝和钛层。 钛层和铝层的沉积可以通过吹扫操作分离，甚至可以在不同的ALD室中进行。 功函数层可以包括交替的钛层和一组铝层，由此形成纳米层状结构。 因此，可以根据需要在功函数层的厚度上控制和改变钛与铝的比例。 例如，工作功能层可以在面向栅极电介质的表面处富含钛，以便减少或防止铝扩散到栅极电介质中。

    METHODS FOR DEPOSITING AN ALUMINUM OXIDE LAYER OVER GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS
    4.
    发明申请
    METHODS FOR DEPOSITING AN ALUMINUM OXIDE LAYER OVER GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS 审中-公开
    用于在整体电路制造中沉积锗永磁体的氧化铝层的方法

    公开(公告)号：US20150093914A1

    公开(公告)日：2015-04-02

    申请号：US14044514

    申请日：2013-10-02

    Applicant: Intermolecular ,  GLOBALFOUNDRIES, Inc.

    Inventor： Bin Yang ,  Abhijit Pethe ,  Albert Lee ,  Amol Joshi ,  Ashish Bodke ,  Kevin Kashefi ,  Salil Mujumdar

    IPC: H01L21/02

    CPC classification number: H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/2807 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeOx layer formed thereon and exposing the semiconductor substrate to first and second atomic layer deposition (ALD) processes. The first ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a first oxygen-containing precursor. The second ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a second oxygen-containing precursor.

    Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括形成在其上的GeO x层的锗基半导体衬底，并将半导体衬底暴露于第一和第二原子层沉积（ALD）工艺。 第一ALD工艺包括将半导体衬底暴露于包含铝的第一气态前体，并将半导体衬底暴露于包含第一含氧前体的第二气态前体。 第二ALD工艺包括将半导体衬底暴露于包含铝的第一气态前体，并将半导体衬底暴露于包含第二含氧前体的第二气态前体。

    DEPOSITION OF TITANIUM-ALUMINUM LAYERS
    5.
    发明申请
    DEPOSITION OF TITANIUM-ALUMINUM LAYERS 有权
    钛 - 铝层的沉积

    公开(公告)号：US20150279680A1

    公开(公告)日：2015-10-01

    申请号：US14242215

    申请日：2014-04-01

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kevin Kashefi ,  Ashish Bodke

    IPC: H01L21/28 ,  H01L29/66 ,  H01L21/285 ,  H01L29/49

    CPC classification number: H01L21/28088 ,  H01L21/28562 ,  H01L21/76846 ,  H01L29/4966 ,  H01L29/66568 ,  H01L29/6659

    Abstract: Transistors having a work function layer and methods of fabricating thereof are disclosed herein. The work function layer includes aluminum and titanium layers which are deposited in separate atomic layer deposition (ALD) operations. The depositions of the titanium layers and the aluminum layers may be separated by a purge operation or even performed in different ALD chambers. The work function layer may include alternating sets of titanium layers and sets of aluminum layers, thereby forming a nanolaminate structure. As such, a ratio of titanium to aluminum may be controlled and varied as needed throughout the thickness of the work function layer. For example, the work function layer may be titanium rich at the surface facing the gate dielectric in order to reduce or prevent diffusion of aluminum into the gate dielectric.

    Abstract translation: 具有功函数层的晶体管及其制造方法在此公开。 功函数层包括以单独的原子层沉积（ALD）操作沉积的铝和钛层。 钛层和铝层的沉积可以通过吹扫操作分离，甚至可以在不同的ALD室中进行。 功函数层可以包括交替的钛层和一组铝层，由此形成纳米层状结构。 因此，可以根据需要在功函数层的厚度上控制和改变钛与铝的比例。 例如，工作功能层可以在面向栅极电介质的表面处富含钛，以便减少或防止铝扩散到栅极电介质中。

    METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS
    7.
    发明申请
    METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS 有权
    用于CMOS应用和结果产品的晶体管器件的门结构的方法

    公开(公告)号：US20150061027A1

    公开(公告)日：2015-03-05

    申请号：US14017485

    申请日：2013-09-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

    IPC: H01L27/092 ,  H01L21/28

    CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

    Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

    Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

    Methods of forming gate structures for transistor devices for CMOS applications
    8.
    发明授权
    Methods of forming gate structures for transistor devices for CMOS applications 有权
    为CMOS应用形成晶体管器件的栅极结构的方法

    公开(公告)号：US09105497B2

    公开(公告)日：2015-08-11

    申请号：US14017485

    申请日：2013-09-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

    IPC: H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

    Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

    Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

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