公开(公告)号：US20150115371A1

公开(公告)日：2015-04-30

申请号：US14519215

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael GANZ ,  Bingwu LIU ,  Johannes Marinus VAN MEER ,  Sruthi MURALIDHARAN

IPC: H01L29/78 ,  H01L21/3105 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/324 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/266 ,  H01L21/268 ,  H01L21/31055 ,  H01L21/32139 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7851 ,  H01L29/7854

Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.

Abstract translation: 本发明提供一种形成半导体结构的方法，其包括：提供具有半导体衬底的中间半导体结构，具有与所述鳍的至少一部分接触的EG氧化物层的鳍和设置在所述鳍的一部分上的栅叠层 翅膀 在所述鳍片的不位于所述栅叠层下方的部分上形成氮化硅层; 并且在形成氮化硅层之后，在中间半导体结构上执行一个或多个离子注入步骤。 本发明还提供一种形成半导体结构的方法，包括：提供具有半导体衬底的中间半导体结构，具有与所述鳍的至少一部分接触的EG氧化物层的鳍和设置在所述鳍上的栅极材料; 在中间半导体结构的鳍和栅极材料之上形成包括氧化物层的栅堆叠硬掩模; 在栅堆叠硬掩模的氧化物层上形成氮化硅阻挡层; 执行一个或多个栅极堆叠硬掩模图案化步骤; 从不在闸门下方的翅片的部分去除EG氧化物层; 并且在从位于栅极下方的鳍片的部分去除EG氧化物层之后，执行一个或多个离子注入步骤。

公开(公告)号：US20150249129A1

公开(公告)日：2015-09-03

申请号：US14716045

申请日：2015-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laegu KANG ,  Vara Govindeswara Reddy VAKADA ,  Michael GANZ ,  Yi QI ,  Puneet KHANNA ,  Sri Charan VEMULA ,  Srikanth SAMAVEDAM

IPC: H01L29/06 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/0692 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66651

Abstract: A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.

Abstract translation: 提供了在场氧化物和外延生长的硅之间形成具有受控步长的SSRW FET的方法以及所得到的器件。 实施例包括在衬底上提供SiN层，通过SiN层形成第一，第二和第三间隔的场区氧化物的STI区域并进入衬底，通过受控的消光去除每个STI区域的场氧化物的顶部部分，去除 SiN层，在第一和第二STI区域之间的衬底中形成n型区域和在第二和第三STI区域之间的衬底中的p型区域，并且在衬底上在n上外延生长Si基层 型和p型区。

公开(公告)号：US20170263733A1

公开(公告)日：2017-09-14

申请号：US15608283

申请日：2017-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael GANZ ,  Bingwu LIU ,  Johannes Marinus VAN MEER ,  Sruthi MURALIDHARAN

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/02 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/268 ,  H01L21/3105

CPC classification number: H01L21/324 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/266 ,  H01L21/268 ,  H01L21/31055 ,  H01L21/32139 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7851 ,  H01L29/7854

Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.

公开(公告)号：US20160181092A1

公开(公告)日：2016-06-23

申请号：US15058669

申请日：2016-03-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael GANZ

IPC: H01L21/02 ,  H01L27/02 ,  H01L29/66 ,  G06F17/50

CPC classification number: H01L21/02362 ,  G06F17/505 ,  G06F2217/02 ,  H01L21/0217 ,  H01L27/0207 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (FinFET)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the FinFET device to mitigate damage during subsequent processing. The nitride spacer is deposited before the block layers to protect the oxide on top of a set of gates in an open area of the FinFET device uncovered by a photoresist. The oxide on top of each gate will be preserved throughout all of the block layers to provide hardmask protection during subsequent source/drain epitaxial layering. Furthermore, the fins that are open and uncovered by the photoresist or the set of gates remain protected by the nitride spacer. Accordingly, fin erosion caused by amorphization of the fins exposed to resist strip processes is prevented, resulting in improved device yield.