公开(公告)号：US20190221661A1

公开(公告)日：2019-07-18

申请号：US15869541

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Zhao ,  Ming Hao Tang ,  Haiting Wang ,  Rui Chen ,  Yuping Ren ,  Hui Zang ,  Scott H. Beasor ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/265 ,  H01L27/11 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/28 ,  H01L29/423

Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.

公开(公告)号：US10600914B2

公开(公告)日：2020-03-24

申请号：US15869541

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Zhao ,  Ming Hao Tang ,  Haiting Wang ,  Rui Chen ,  Yuping Ren ,  Hui Zang ,  Scott H. Beasor ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L27/11 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.

公开(公告)号：US20190259708A1

公开(公告)日：2019-08-22

申请号：US15898606

申请日：2018-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ming Hao Tang ,  Yuping Ren ,  Rui Chen ,  Bradley Morgenfeld ,  Zheng G. Chen

IPC: H01L23/544 ,  G03F9/00 ,  G03F7/20 ,  H01L21/66 ,  G01N21/95

Abstract: This disclosure relates to a structure for aligning layers of an integrated circuit (IC) structure that may include a first dielectric layer positioned above a semiconductor substrate having one or more active devices, a trench stop layer positioned above the first dielectric layer, a second dielectric layer positioned above the trench stop layer, and a plurality of metal-filled marking trenches extending vertically through the second dielectric layer and the trench stop layer and at least partially into the first dielectric layer. The metal-filled trenches are electrically isolated from any active devices contained in the IC.

公开(公告)号：US10566291B2

公开(公告)日：2020-02-18

申请号：US15898606

申请日：2018-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ming Hao Tang ,  Yuping Ren ,  Rui Chen ,  Bradley Morgenfeld ,  Zheng G. Chen

IPC: H01L23/544 ,  G03F9/00 ,  G03F7/20 ,  G01N21/95 ,  H01L21/66

Abstract: This disclosure relates to a structure for aligning layers of an integrated circuit (IC) structure that may include a first dielectric layer positioned above a semiconductor substrate having one or more active devices, a trench stop layer positioned above the first dielectric layer, a second dielectric layer positioned above the trench stop layer, and a plurality of metal-filled marking trenches extending vertically through the second dielectric layer and the trench stop layer and at least partially into the first dielectric layer. The metal-filled trenches are electrically isolated from any active devices contained in the IC.

公开(公告)号：US10453751B2

公开(公告)日：2019-10-22

申请号：US15432016

申请日：2017-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaofeng Qiu ,  Michael V. Aquilino ,  Patrick D. Carpenter ,  Jessica Dechene ,  Ming Hao Tang ,  Haigou Huang ,  Huy Cao

IPC: H01L29/78 ,  H01L21/8234 ,  H01L23/535 ,  H01L21/768 ,  H01L29/423 ,  H01L27/088 ,  H01L21/033 ,  H01L21/311 ,  H01L29/417

Abstract: A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.