公开(公告)号：US10453751B2

公开(公告)日：2019-10-22

申请号：US15432016

申请日：2017-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaofeng Qiu ,  Michael V. Aquilino ,  Patrick D. Carpenter ,  Jessica Dechene ,  Ming Hao Tang ,  Haigou Huang ,  Huy Cao

IPC: H01L29/78 ,  H01L21/8234 ,  H01L23/535 ,  H01L21/768 ,  H01L29/423 ,  H01L27/088 ,  H01L21/033 ,  H01L21/311 ,  H01L29/417

Abstract: A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.

公开(公告)号：US10014298B1

公开(公告)日：2018-07-03

申请号：US15844840

申请日：2017-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haigou Huang ,  Xiaofeng Qiu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/49 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L27/0886 ,  H01L21/28123 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/78651

Abstract: In a method for forming an integrated circuit (IC) structure, which incorporates multiple field effect transistors (FETs) with discrete replacement metal gates (RMGs) and replacement metal contacts (RMCs), gate cut trench(es) and contact cut trench(es) are formed at the same process level. These trench(es) are then filled at the same time with the same isolation material to form gate cut isolation region(s) for electrically isolating adjacent RMGs and contact cut isolation region(s) for electrically isolating adjacent RMCs, respectively. The selected isolation material can be a low-K isolation material for optimal performance. Furthermore, since the same process step is used to fill both types of trenches, only a single chemical mechanical polishing (CMP) process is needed to remove the isolation material from above the gate level, thereby minimizing gate height loss and process variation. Also disclosed herein is an IC structure formed according to the method.

公开(公告)号：US09922972B1

公开(公告)日：2018-03-20

申请号：US15491222

申请日：2017-04-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaofeng Qiu ,  Haigou Huang ,  Chang Ho Maeng

IPC: H01L21/461 ,  H01L23/12 ,  H01L23/043 ,  H01L27/088 ,  H01L21/02 ,  H01L21/308 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823475

Abstract: A lithography method and accompanying structure for decreasing the critical dimension (CD) and improving the CD uniformity within semiconductor devices uses a layer of silicon carbide as an embedded blocking mask for defining semiconductor architectures, including contact trench openings to form trench silicide contacts.

公开(公告)号：US09911736B1

公开(公告)日：2018-03-06

申请号：US15622949

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haigou Huang ,  Xiaofeng Qiu

IPC: H01L21/28 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/762

CPC classification number: H01L21/31053 ,  H01L21/28123 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: In a method for forming an integrated circuit (IC) structure, which incorporates multiple field effect transistors (FETs) with discrete replacement metal gates (RMGs) and replacement metal contacts (RMCs), gate cut trench(es) and contact cut trench(es) are formed at the same process level. These trench(es) are then filled at the same time with the same isolation material to form gate cut isolation region(s) for electrically isolating adjacent RMGs and contact cut isolation region(s) for electrically isolating adjacent RMCs, respectively. The selected isolation material can be a low-K isolation material for optimal performance. Furthermore, since the same process step is used to fill both types of trenches, only a single chemical mechanical polishing (CMP) process is needed to remove the isolation material from above the gate level, thereby minimizing gate height loss and process variation. Also disclosed herein is an IC structure formed according to the method.