公开(公告)号：US20170162234A1

公开(公告)日：2017-06-08

申请号：US14961484

申请日：2015-12-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramesh Raghavan ,  Balaji Jayaraman ,  Janakiraman Viraraghavan ,  Thejas Kempanna ,  Rajesh Reddy Tummuru ,  Toshiaki Kirihata

IPC: G11C7/06 ,  G11C7/18 ,  G11C5/14 ,  G11C7/12

CPC classification number: G11C5/06 ,  G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/1012 ,  G11C7/12 ,  G11C7/18 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002 ,  G11C2211/4013

Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.

公开(公告)号：US09659604B1

公开(公告)日：2017-05-23

申请号：US14961484

申请日：2015-12-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramesh Raghavan ,  Balaji Jayaraman ,  Janakiraman Viraraghavan ,  Thejas Kempanna ,  Rajesh Reddy Tummuru ,  Toshiaki Kirihata

IPC: G11C11/56 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C5/14

CPC classification number: G11C5/06 ,  G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/1012 ,  G11C7/12 ,  G11C7/18 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002 ,  G11C2211/4013

Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.

公开(公告)号：US09786333B2

公开(公告)日：2017-10-10

申请号：US15478820

申请日：2017-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramesh Raghavan ,  Balaji Jayaraman ,  Janakiraman Viraraghavan ,  Thejas Kempanna ,  Rajesh Reddy Tummuru ,  Toshiaki Kirihata

IPC: G11C11/56 ,  G11C5/06 ,  G11C5/14 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C5/06 ,  G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/1012 ,  G11C7/12 ,  G11C7/18 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002 ,  G11C2211/4013

Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.

公开(公告)号：US20170206938A1

公开(公告)日：2017-07-20

申请号：US15478820

申请日：2017-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ramesh Raghavan ,  Balaji Jayaraman ,  Janakiraman Viraraghavan ,  Thejas Kempanna ,  Rajesh Reddy Tummuru ,  Toshiaki Kirihata

IPC: G11C5/06 ,  G11C7/06 ,  G11C7/10 ,  G11C5/14

CPC classification number: G11C5/06 ,  G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/1012 ,  G11C7/12 ,  G11C7/18 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002 ,  G11C2211/4013

Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.