公开(公告)号：US09318415B2

公开(公告)日：2016-04-19

申请号：US14148532

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephen M Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

IPC: H01L23/48 ,  H01L27/06 ,  H01L25/18 ,  H01L21/02 ,  H01L23/00 ,  H01L25/00 ,  H01L29/66 ,  H01L29/861 ,  H01L29/872 ,  H01L23/522 ,  H01L23/532 ,  H01L27/01

CPC classification number: H01L23/481 ,  H01L21/02667 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/53238 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L27/016 ,  H01L27/0688 ,  H01L29/66984 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

Abstract: An integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate.

Abstract translation: 集成电路和方法包括：衬底，单片集成在衬底上的多个半导体器件层，以及具有互连多个半导体器件层的通孔的金属布线层。 半导体器件层没有与衬底接合或结合界面。

公开(公告)号：US09275936B2

公开(公告)日：2016-03-01

申请号：US14148573

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

IPC: H01L21/02 ,  H01L23/48 ,  H01L27/06 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L29/66 ,  H01L29/861 ,  H01L29/872 ,  H01L23/522 ,  H01L23/532 ,  H01L27/01

CPC classification number: H01L23/481 ,  H01L21/02667 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/53238 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L27/016 ,  H01L27/0688 ,  H01L29/66984 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

Abstract: A method of fabricating a monolithic integrated circuit using a single substrate, the method including forming a first semiconductor layer from a substrate, fabricating semiconductor devices on the substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.

Abstract translation: 一种使用单个衬底制造单片集成电路的方法，所述方法包括从衬底形成第一半导体层，在衬底上制造半导体器件，在半导体器件上制造至少一个金属布线层，形成至少一个电介质层 与所述至少一个金属布线层整体接触，形成通过所述至少一个电介质层的接触开口，以暴露所述至少一个金属布线层的区域，从所述基板一体地形成所述介电层上的第二半导体层， 并且通过所述接触开口与所述至少一个金属布线层接触，并且在所述第二半导体层中形成多个非线性半导体器件。

公开(公告)号：US09332628B2

公开(公告)日：2016-05-03

申请号：US14739703

申请日：2015-06-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/02 ,  H01L21/768 ,  H05K1/03

CPC classification number: H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.