公开(公告)号：US20140353835A1

公开(公告)日：2014-12-04

申请号：US13903283

申请日：2013-05-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Moosung M. CHAE ,  Errol Todd RYAN ,  Nicholas Vincent LICAUSI ,  Christian WITT ,  Ailian ZHAO ,  Ming HE ,  Sean X. LIN ,  Xunyuan ZHANG ,  Kunaljeet TANWAR

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76831 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76843 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.

Abstract translation: 提供了一种用于在半导体制造期间减少超低k层的自形成势垒的污染的方法的方法。 一方面，一种方法包括：提供包含至少一个沟槽的固化的超低k膜，并且用孔填充材料填充膜的孔; 在沟槽的表面去除暴露的孔隙填充材料以形成暴露的孔; 并在沟槽的表面上形成自形成阻挡层。

公开(公告)号：US20160379872A1

公开(公告)日：2016-12-29

申请号：US14752210

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal KAMINENI ,  Nicholas Vincent LICAUSI ,  Shariq SIDDIQUI ,  Jeremy Austin WAHL

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76834 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76814 ,  H01L23/535

Abstract: A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation.

Abstract translation: 一种方法可以包括在半导体结构中形成接触沟槽，使得接触沟槽延伸到接触层，形成包括使用硬掩模层，并用牺牲材料层填充接触沟槽，牺牲材料层形成在触点上 形成。 半导体结构可以包括在接触层上的牺牲材料层。

公开(公告)号：US20170033224A1

公开(公告)日：2017-02-02

申请号：US14812653

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent LICAUSI ,  Zhenyu HU ,  Hong YU ,  Jinping LIU

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L29/7853 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/66795

Abstract: A method can include performing an etching process to define a fin trench having a first depth, the first depth being less that a target height of fin. A method can also include forming a layer to protect sidewalls defining the fin trench. A method can also include performing a second etching process to increase a depth of fin trench.

Abstract translation: 一种方法可以包括执行蚀刻工艺以限定具有第一深度的翅片沟槽，第一深度小于翅片的目标高度。 方法还可以包括形成层以保护限定翅片沟槽的侧壁。 方法还可以包括执行第二蚀刻工艺以增加散热片沟槽的深度。

公开(公告)号：US20140353802A1

公开(公告)日：2014-12-04

申请号：US13903802

申请日：2013-05-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent LICAUSI ,  Errol Todd RYAN ,  Ming HE ,  Moosung M. CHAE ,  Kunaljeet TANWAR ,  Larry ZHAO ,  Christian WITT ,  Ailian ZHAO ,  Sean X. LIN ,  Xunyuan ZHANG

IPC: H01L21/314 ,  H01L21/32 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L21/314 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L29/06 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

Abstract translation: 提供了一种在制造期间减少对超低k层的损伤的方法的方法。 一方面，一种方法包括：提供含有填充有孔填充材料的孔的固化的超低k膜; 以及改变超低k膜的暴露表面以在超低k膜中提供改性层。 在另一方面，提供一种在超低k膜的表面上包含改性层的半导体器件。

公开(公告)号：US20180174894A1

公开(公告)日：2018-06-21

申请号：US15379605

申请日：2016-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume BOUCHE ,  Nicholas Vincent LICAUSI

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/302 ,  H01L21/308 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

Abstract: A semiconductor cell includes a dielectric layer. An array of at least four parallel metal lines is disposed within the dielectric layer, the metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines, the line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. An overall cell height of the cell is substantially equal to an integer multiple of a plurality of cell tracks, each cell track being a minimum pitch of the cell. The minimum pitch being defined by the minimum line width plus the minimum line spacer width. The minimum pitch is equal to or less than 36 nm. Not all of the line widths are substantially equal and every other line spacer width is substantially equal.

公开(公告)号：US20170365509A1

公开(公告)日：2017-12-21

申请号：US15182794

申请日：2016-06-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol Todd RYAN ,  Nicholas Vincent LICAUSI

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76814 ,  H01L21/02126 ,  H01L21/31111 ,  H01L21/76825 ,  H01L21/76826

Abstract: Devices and methods of fabricating integrated circuit devices for forming assymetric line/space with barrierless metallization are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, a dielectric matrix, and a hardmask, the dielectric matrix including a set of trenches etched into the dielectric matrix and a set of dielectric fins comprising the dielectric matrix, wherein the set of trenches and the set of dielectric fins are of equal width; damaging an inner surface of each trench of the set of trenches; etching the damaged material of the trenches removing the damaged material of the dielectric matrix; removing the hardmask; and metallizing the trenches by depositing a metal directly on the dielectric matrix with no barrier between the metal and the dielectric matrix after the etching. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US20180174896A1

公开(公告)日：2018-06-21

申请号：US15800551

申请日：2017-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas Vincent LICAUSI ,  Guillaume BOUCHE

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286

Abstract: A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. The metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines. The line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. The array of metal lines includes a signal line having a continuity cut disposed across its entire line width and a power line adjacent the signal line. The power line has a line width that is greater than twice the minimum line width. The power line has a notch disposed partially across its line width. The notch is aligned with the continuity cut in a direction perpendicular to the longitudinal direction of the metal lines.

公开(公告)号：US20180174895A1

公开(公告)日：2018-06-21

申请号：US15379707

申请日：2016-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent LICAUSI ,  Guillaume BOUCHE

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

Abstract: A method includes providing a semiconductor structure having a mandrel layer and a hardmask layer disposed above a dielectric layer. A mandrel cell is patterned into the mandrel layer. An opening is etched into the hardmask layer. The opening is self-aligned with a sidewall of the mandrel. A refill layer is disposed over the structure and recessed down to a level that is below a top surface of the hardmask layer to form an opening plug that covers a bottom of the opening. The mandrel cell is utilized to form a metal line cell into the dielectric layer, the metal line cell having metal lines and a minimum line cell pitch. The opening plug is utilized to form a continuity cut in a metal line of the metal line cell. The continuity cut has a length that is larger than the minimum line cell pitch.

公开(公告)号：US20140353805A1

公开(公告)日：2014-12-04

申请号：US13903618

申请日：2013-05-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol Todd RYAN ,  Moosung M. CHAE ,  Larry ZHAO ,  Kunaljeet TANWAR ,  Nicholas Vincent LICAUSI ,  Christian WITT ,  Ailian ZHAO ,  Ming HE ,  Sean X. LIN ,  Xunyuan ZHANG

IPC: H01L21/3105 ,  H01L23/00

CPC classification number: H01L21/02101 ,  H01L21/02063 ,  H01L21/76814

Abstract: A process is provided for the removal of contaminants from a semiconductor device, for example, removing contaminants from pores of an ultra-low k film. In one aspect, a method includes: providing a dielectric layer with contaminant-containing pores and exposing the dielectric layer to a supercritical fluid. The supercritical fluid can dissolve and remove the contaminants. In another aspect, an intermediate semiconductor device structure is provided that contains a dielectric layer with contaminant-containing pores and a supercritical fluid within the pores. In another aspect, a semiconductor device structure with a dielectric layer containing uncontaminated pores is provided.

Abstract translation: 提供了用于从半导体器件去除污染物的方法，例如从超低k膜的孔中除去污染物。 一方面，一种方法包括：向电介质层提供含有污染物的孔，并将介电层暴露于超临界流体。 超临界流体可以溶解和去除污染物。 在另一方面，提供了一种中间半导体器件结构，其包含具有含污染孔的电介质层和孔内的超临界流体。 另一方面，提供了具有含有未污染孔的电介质层的半导体器件结构。