公开(公告)号：US09418745B1

公开(公告)日：2016-08-16

申请号：US14661383

申请日：2015-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiang Chen ,  Toshiaki Kirihata ,  Derek H. Leu ,  Dan Moy

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/20 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C16/10 ,  G11C16/20 ,  G11C16/26

Abstract: A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read after each of write cycle. Each multi-time programmable memory cell includes a series connection of a first transistor and a second transistor. The method includes writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells. Then, using the write circuit, a rebalancing of a state of a parameter associated with one or more the first transistor or second transistor, at each the select memory cell, is performed. Then, an erasing cycle is performed, at each the rebalanced select memory cell, the written initial bit value. In one embodiment, the erasing cycle may first be performed prior to rebalancing. The rebalancing and erasing are to be performed prior to each bit value write cycle.

Abstract translation: 一种操作双晶体管，多时间可编程存储器（MTPM）存储单元的系统和方法，其确保在每个写周期之后读取的位值的精确再现性。 每个多时间可编程存储器单元包括第一晶体管和第二晶体管的串联连接。 该方法包括将选择存储单元位置处的写入电路写入到一个或多个选择存储单元的初始位值。 然后，使用写入电路，执行在每个选择存储单元处与一个或多个第一晶体管或第二晶体管相关联的参数的状态的再平衡。 然后，在每个重新平衡选择存储单元处执行擦除周期，写入的初始位值。 在一个实施例中，可以在重新平衡之前首先执行擦除循环。 在每个位值写周期之前执行重新平衡和擦除。

公开(公告)号：US09497027B2

公开(公告)日：2016-11-15

申请号：US14293306

申请日：2014-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiang Chen ,  Derek H. Leu ,  Toshiaki Kirihata ,  Sami Rosenblatt

IPC: G06F11/30 ,  H04L9/32 ,  G11C16/04 ,  G11C17/16 ,  G06F12/14 ,  G09C1/00 ,  G11C7/24 ,  G11C11/56

CPC classification number: H04L9/3278 ,  G06F12/1408 ,  G06F12/1425 ,  G09C1/00 ,  G11C7/24 ,  G11C11/5692 ,  G11C16/0491 ,  G11C16/22 ,  G11C17/16

Abstract: Described are a hardware encryption engine, and secret key registration and authentication system recoverable binary bit using knowing an initial secret key stored in the master system. The secret key is overwritten in each authentication, updating it to the master and encryption engine independently. The secret key over write command can be preferably given to the chip as a CHG, and the non recoverable binary bit from the sense amplifier is used for response.

Abstract translation: 描述了硬件加密引擎，以及使用知道存储在主系统中的初始秘密密钥的秘密密钥注册和认证系统可恢复的二进制位。 每个身份验证中都会覆盖秘密密钥，将其独立更新为主服务器和加密引擎。 秘密密钥写入命令可以优选地作为CHG被提供给芯片，并且来自读出放大器的不可恢复的二进制位用于响应。