公开(公告)号：US20170301551A1

公开(公告)日：2017-10-19

申请号：US15099641

申请日：2016-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Donghun KANG ,  Balaji KANNAN ,  Jinping LIU

IPC: H01L21/308 ,  H01L21/3065 ,  H01L21/306 ,  H01L27/092 ,  H01L21/285

CPC classification number: H01L21/3085 ,  H01L21/28556 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092

Abstract: A method of fabricating multi Vth devices and the resulting device are disclosed. Embodiments include forming a high-k dielectric layer over a substrate; forming a first TiN layer, a first barrier layer, a second TiN layer, a second barrier layer, and a third TiN layer consecutively over the high-k dielectric layer; forming a first masking layer over the third TiN layer in a first region; removing the third TiN layer in second and third regions, exposing the second barrier layer in the second and third regions; removing the first masking layer; removing the exposed second barrier layer; forming a second masking layer over the third TiN layer in the first region and the second TiN layer in the second regions; removing the second TiN layer in the third region, exposing the first barrier layer in the third region; removing the second masking layer; and removing the exposed first barrier layer.

公开(公告)号：US20170250117A1

公开(公告)日：2017-08-31

申请号：US15055826

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji KANNAN ,  Unoh KWON ,  Siddarth KRISHNAN ,  Takashi ANDO ,  Vijay NARAYANAN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/324 ,  H01L21/225

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

Abstract: Semiconductor device fabrication methods are provided which include: providing a structure with at least one region and including a dielectric layer disposed over a substrate; forming a multilayer stack structure including a threshold-voltage adjusting layer over the dielectric layer, the multilayer stack structure including a first threshold-voltage adjusting layer in a first region of the at least one region, and a second threshold-voltage adjusting layer in a second region of the at least one region; and annealing the structure to define a varying threshold voltage of the at least one region, the annealing facilitating diffusion of at least one threshold voltage adjusting species from the first threshold-voltage adjusting layer and the second threshold-voltage adjusting layer into the dielectric layer, where a threshold voltage of the first region is independent of the threshold voltage of the second region.

公开(公告)号：US20190393221A1

公开(公告)日：2019-12-26

申请号：US16562481

申请日：2019-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji KANNAN ,  Ayse M. OZBEK ,  Tao CHU ,  Bala HARAN ,  Vishal CHHABRA ,  Katsunori ONISHI ,  Guowei XU

IPC: H01L27/092 ,  H01L21/027 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L27/02 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

公开(公告)号：US20190115346A1

公开(公告)日：2019-04-18

申请号：US15783549

申请日：2017-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji KANNAN ,  Ayse M. OZBEK ,  Tao CHU ,  Bala HARAN ,  Vishal CHHABRA ,  Katsunori ONISHI ,  Guowei XU

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/311 ,  H01L21/027 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

公开(公告)号：US20190027578A1

公开(公告)日：2019-01-24

申请号：US15654234

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bala HARAN ,  Ruilong XIE ,  Balaji KANNAN ,  Katsunori ONISHI ,  Vimal K. KAMINENI

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/285

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.