公开(公告)号：US10347740B2

公开(公告)日：2019-07-09

申请号：US15367366

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Min-hwa Chi ,  Edmund Kenneth Banghart

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16

Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

公开(公告)号：US09679990B2

公开(公告)日：2017-06-13

申请号：US14454778

申请日：2014-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edmund Kenneth Banghart ,  Mitsuhiro Togo ,  Shesh Mani Pandey

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.

公开(公告)号：US09583625B2

公开(公告)日：2017-02-28

申请号：US14523548

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xusheng Wu ,  Min-hwa Chi ,  Edmund Kenneth Banghart

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/66537 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

Abstract translation: 提供一种形成具有低掺杂和高掺杂有源部分的FinFET鳍片的方法和/或具有用于Vt调谐和多Vt方案的锥形侧壁的FinFET鳍片以及所得到的器件。 实施例包括形成Si翅片，所述Si翅片具有顶部活性部分和底部活性部分; 在Si翅片的顶表面上形成硬掩模; 在所述Si翅片的相对侧上形成氧化物层; 将掺杂剂注入到Si鳍中; 凹陷氧化物层以露出Si鳍的有效顶部; 蚀刻Si翅片的顶部活性部分以形成垂直侧壁; 形成覆盖每个垂直侧壁的氮化物间隔物; 凹陷凹陷的氧化物层以露出Si鳍的活性底部; 并使Si翅片的活性底部部分变细。

公开(公告)号：US09570291B2

公开(公告)日：2017-02-14

申请号：US14798796

申请日：2015-07-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shishir Ray ,  Sandeep Gaan ,  Sheldon Meyers ,  Nisha Pillai ,  Edmund Kenneth Banghart ,  Kyle Jung

IPC: G03F7/26 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/1604 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/31058

Abstract: Semiconductor substrates and methods for processing semiconductor substrates are provided. A method for processing a semiconductor substrate includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.

Abstract translation: 提供半导体衬底和半导体衬底的处理方法。 一种用于处理半导体衬底的方法包括提供在外边缘和中心区域之间具有外边缘，中心区域和周边区域的半导体衬底。 半导体衬底也具有上表面。 该方法包括在周边区域的半导体衬底的上表面上形成无定形材料。 此外，该方法包括照射半导体衬底的上表面，其中非晶态材料抑制在半导体衬底的外边缘处的裂纹。

公开(公告)号：US20170018426A1

公开(公告)日：2017-01-19

申请号：US14798796

申请日：2015-07-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shishir Ray ,  Sandeep Gaan ,  Sheldon Meyers ,  Nisha Pillai ,  Edmund Kenneth Banghart ,  Kyle Jung

IPC: H01L21/02 ,  H01L29/16

CPC classification number: H01L29/1604 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/31058

Abstract: Semiconductor substrates and methods for fabricating integrated circuits are provided. A method for fabricating an integrated circuit includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.

Abstract translation: 提供半导体基板和用于制造集成电路的方法。 一种用于制造集成电路的方法包括提供在外边缘和中心区域之间具有外边缘，中心区域和周边区域的半导体基板。 半导体衬底也具有上表面。 该方法包括在周边区域的半导体衬底的上表面上形成无定形材料。 此外，该方法包括照射半导体衬底的上表面，其中非晶态材料抑制在半导体衬底的外边缘处的裂纹。

公开(公告)号：US09087860B1

公开(公告)日：2015-07-21

申请号：US14264179

申请日：2014-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edmund Kenneth Banghart ,  Yanxiang Liu ,  Shesh Mani Pandey

IPC: H01L29/76 ,  H01L29/66 ,  H01L27/085 ,  H01L21/76 ,  H01L29/06 ,  H01L29/167 ,  H01L21/265 ,  H01L29/10

CPC classification number: H01L29/66803 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0638 ,  H01L29/1083 ,  H01L29/167

Abstract: Methods are provided for fabricating a fin-type field effect transistor(s), having a channel region within a fin. The methods include: establishing a protective material above an upper surface of the fin, and an isolation material adjacent to at least one sidewall of the fin, the isolation material being recessed down from the upper surface of the fin, for instance, for approximately a height of the channel region within the fin; and providing a punch-through stop dopant region within the fin below the channel region, the providing including implanting a punch-through stop dopant into the isolation material and laterally diffusing the punch-through stop dopant from the isolation material into the fin to form the punch-through stop region within the fin beneath the channel region.

Abstract translation: 提供了用于制造翅片式场效应晶体管的方法，其具有鳍内的沟道区。 所述方法包括：在翅片的上表面上方建立保护材料，以及邻近翅片的至少一个侧壁的隔离材料，隔离材料从翅片的上表面向下凹下，例如约 翅片内的通道区域的高度; 以及在通道区域下方的翅片内提供穿通止动掺杂剂区域，所述提供包括将穿通阻止掺杂剂注入到隔离材料中并将穿通阻止掺杂剂横向扩散到隔离材料进入翅片以形成 在通道区域下方的翅片内的穿通停止区域。